UCSB SoC Design and Test Lab

Welcome to UCSB SoC design and test lab! This lab was founded by Professor Kwang-Ting (Tim) Cheng in 1993. We focus on developing methodologies, algorithms, techniques, and tools for validating, verifying, testing, and synthesizing deep sub-micron (DSM) system-on-chip (SoC) devices as well as flexible electronics.

News and Announcements

ASP-DAC 2012

Prof. Cheng and Peter will be at the Asia and South Pacific Design Automation Conference (ASP-DAC) in Sydney to present one invited and two regular papers.

GSRC Annual Review

Prof. Cheng, Ming, and Amirali will present research updates at the GSRC annual review November 16-17, 2011.

HLDVT 2011

Peter will present "Coverage Discounting: A Generalized Approach for Testbench Qualification" at HLDVT'11 on Thursday, November 10th.

New Site

Our new website is live!

Recent Publications

Coverage Discounting: A Generalized Approach for Testbench Qualification

Lisherness, P., and K-T(T). Cheng, "Coverage Discounting: A Generalized Approach for Testbench Qualification", High Level Design Validation and Test Workshop, 2011. HLDVT 2011. IEEE International, 11/2011.

HLDVT11.pdf

Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip

Shamshiri, S., and K T(T). Cheng, "Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip", Computers, IEEE Transactions on, vol. 60, no. 9, pp. 1246 -1259, 09/2011.

2011_TC_Saeed.pdf

Time-Multiplexed Online Checking

Gao, M., H-M(S). Chang, P. Lisherness, and K T(T). Cheng, "Time-Multiplexed Online Checking", Computers, IEEE Transactions on, vol. 60, no. 9, pp. 1300 -1312, 09/2011.

2011_09_TMOC.pdf

Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers

Chang, H-M(S)., and K T(T). Cheng, "Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers", Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pp. 759 -764, 06/2011.

2011_06_DAC2011_ADCArraySpec.pdf

An all-digital built-in self-test technique for transfer function characterization of RF PLLs

Wang, P-Y., H-M(S). Chang, and K T(T). Cheng, "An all-digital built-in self-test technique for transfer function characterization of RF PLLs", Design, Automation Test in Europe Conference Exhibition (DATE), 2011, pp. 1 -6, 03/2011.

2011_03_DATE2011_PLL_TF_BIST.pdf

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