UCSB SoC Design and Test Lab

Welcome to UCSB SoC design and test lab! This lab was founded by Professor Kwang-Ting (Tim) Cheng in 1993. We focus on developing methodologies, algorithms, techniques, and tools for validating, verifying, testing, and synthesizing deep sub-micron (DSM) system-on-chip (SoC) devices as well as flexible electronics.

News and Announcements

Ming Gao's Ph.D. Defense

Congratulations to Ming on defending his Ph.D. thesis: "Cost Effective Error Detection for SoC Validation and Online Testing"

Posted: Tuesday, May 1, 2012 - 17:07

VTS 2012

Amirali will be at the VLSI Test Symposium in Maui to present our recent work in defect diagnosis in NoC.

Posted: Tuesday, April 17, 2012 - 16:46

DATE 2012

Our visiting scholar Yan Zheng will be at DATE in Dresden to present our recent work in on-chip optical communications.

Posted: Friday, March 9, 2012 - 17:27

ASP-DAC 2012

Prof. Cheng and Peter will be at the Asia and South Pacific Design Automation Conference (ASP-DAC) in Sydney to present one invited and two regular papers.

Improving Validation Coverage Metrics to Account for Limited Observability
Post-Fabrication Reconfiguration for Power-Optimized Tuning of Optically Connected Multi-Core Systems
On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation

Posted: Monday, January 23, 2012 - 15:55

GSRC Annual Review

Prof. Cheng, Ming, and Amirali will present research updates at the GSRC annual review November 16-17, 2011.

Posted: Monday, November 7, 2011 - 11:54

HLDVT 2011

Peter will present "Coverage Discounting: A Generalized Approach for Testbench Qualification" at HLDVT'11 on Thursday, November 10th.

Posted: Monday, November 7, 2011 - 11:52

New Site

Our new website is live!

Posted: Monday, October 3, 2011 - 09:06

Recent Publications

A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers

Chang, H-M(S)., J-L. Huang, D-M. Kwai, K-T. Cheng, and C-W. Wu, "A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 04/2012.

Comprehensive Online Defect Diagnosis in On-Chip Networks

Ghofrani, A., R. Parikh, S. Shamshiri, A. DeOrio, K-T. Cheng, and V. Bertacco, "Comprehensive Online Defect Diagnosis in On-Chip Networks", VLSI Test Symposium, 04/2012.

Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication

Zheng, Y., P. Lisherness, M. Gao, J. Bovington, S. Yang, and K-T(T). Cheng, "Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication", DATE'12: Design Automation and Test Europe, 03/2012.

DATE2012_Optical.pdf

Post-Fabrication Reconfiguration for Power-Optimized Tuning of Optically Connected Multi-Core Systems

Zheng, Y., P. Lisherness, S. Shamshiri, A. Ghofrani, S. Yang, and K-T(T). Cheng, "Post-Fabrication Reconfiguration for Power-Optimized Tuning of Optically Connected Multi-Core Systems", The 17th Asia and South Pacific Design Automation Conference (ASP-DAC '12), 02/2012.

ASPDAC2012_optical.pdf

On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation

Gao, M., P. Lisherness, J-J. Liou, and K-T. Cheng, "On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation", The 17th Asia and South Pacific Design Automation Conference (ASP-DAC '12), Sydney, Australia , IEEE, ACM, 02/2012.

ASPDAC2012_Glitch.pdf

Improving Validation Coverage Metrics to Account for Limited Observability

Lisherness, P., and K-T. Cheng, "Improving Validation Coverage Metrics to Account for Limited Observability", Asia and South Pacific Design Automation Conference, 02/2012.

ASPDAC_Invited.pdf

Coverage Discounting: A Generalized Approach for Testbench Qualification

Lisherness, P., and K-T. Cheng, "Coverage Discounting: A Generalized Approach for Testbench Qualification", High Level Design Validation and Test Workshop, 2011. HLDVT 2011. IEEE International, 11/2011.

HLDVT11.pdf

Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip

Shamshiri, S., and K-T. Cheng, "Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip", Computers, IEEE Transactions on, vol. 60, no. 9, pp. 1246 -1259, 09/2011.

2011_TC_Saeed.pdf

Main menu