UCSB SoC Design and Test Lab

Compact Modeling for Silicon Photonic Heterogeneously Integrated Circuits

Submitted by Yuyang Wang on Mon, 05/22/2017 - 10:13

Z. Zhang, Wu, R., Wang, Y., Zhang, C., Stanton, E. J., Schow, C. L., Cheng, K. - T., and Bowers, J. E., “Compact Modeling for Silicon Photonic Heterogeneously Integrated Circuits”, Journal of Lightwave Technology (JLT), 2017.

A Multiply-Add Engine with Monolithically Integrated 3D Memristor Crossbar/CMOS Hybrid Circuit

Submitted by Miguel Lastras on Sun, 02/26/2017 - 20:35

B. Chakrabarti, Lastras-Montano, M. Angel, Adam, G., Prezioso, M., Hoskins, B., Cheng, K. - T. Tim, and Strukov, D. B., “A Multiply-Add Engine with Monolithically Integrated 3D Memristor Crossbar/CMOS Hybrid Circuit”, Nature Scientific Reports, 2017.

Verification and Trust for Unspecified IP Functionality

Submitted by Nicole Fern on Wed, 02/01/2017 - 18:49

N. Fern and Cheng, K. - T. Tim, “Verification and Trust for Unspecified IP Functionality”, in Hardware IP Security and Trust, P. Mishra, Bhunia, S., and Tehranipoor, M. Springer, 2017.

Detecting Hardware Trojans in Unspecified Functionality Through Solving Satisfiability Problems

Submitted by Nicole Fern on Wed, 02/01/2017 - 18:44

N. Fern, San, I., and Cheng, K. - T. Tim, “Detecting Hardware Trojans in Unspecified Functionality Through Solving Satisfiability Problems”, in Asia and South Pacific Design Automation Conference (ASP-DAC), 2017.

Hiding Hardware Trojan Communication Channels in Partially Specified SoC Bus Functionality

Submitted by Nicole Fern on Wed, 02/01/2017 - 18:37

N. Fern, San, I., Koc, C. Kaya, and Cheng, K. - T. Tim, “Hiding Hardware Trojan Communication Channels in Partially Specified SoC Bus Functionality”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. PP, 2016.

Trojans Modifying Soft-Processor Instruction Sequences Embedded in FPGA Bitstreams

Submitted by Nicole Fern on Wed, 02/01/2017 - 18:27

I. San, Fern, N., Koc, C. Kaya, and Cheng, K. - T. Tim, “Trojans Modifying Soft-Processor Instruction Sequences Embedded in FPGA Bitstreams”, in Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL), 2016.

Compact Modeling and Circuit-Level Simulation of Silicon Nanophotonic Interconnects

Submitted by Rui Wu on Mon, 01/30/2017 - 13:51

R. Wu, Wang, Y., Zhang, Z., Zhang, C., Schow, C., Bowers, J. E., and Cheng, K. - T., “Compact Modeling and Circuit-Level Simulation of Silicon Nanophotonic Interconnects”, in Design, Automation and Test in Europe (DATE), Lausanne, 2017.

3D-DPE: A 3D High-Bandwidth Dot-Product Engine for High-Performance Neuromorphic Computing

Submitted by Miguel Lastras on Wed, 11/30/2016 - 00:42

M. Angel Lastras-Montano, Chakrabarti, B., Strukov, D. B., and Cheng, K. - T., “3D-DPE: A 3D High-Bandwidth Dot-Product Engine for High-Performance Neuromorphic Computing”, Design, Automation and Test in Europe (DATE). Lausanne, Switzerland, 2017.

An Artificial Neural Network Approach for Screening Test Escapes

Submitted by Rui Wu on Wed, 11/09/2016 - 22:02

F. Lin and Cheng, K. - T. Tim, “An Artificial Neural Network Approach for Screening Test Escapes”, Asia and South Pacific Design Automation Conference (ASP-DAC). Chiba/Tokyo, Japan, 2017.

DLPS: Dynamic Laser Power Scaling for Optical Network-on-Chip

Submitted by Rui Wu on Sun, 10/23/2016 - 20:03

F. Lan, Wu, R., Zhang, C., Pan, Y., and Cheng, K. - T. Tim, “DLPS: Dynamic Laser Power Scaling for Optical Network-on-Chip”, in Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba/Tokyo, Japan, 2017.