UCSB SoC Design and Test Lab

Welcome to UCSB SoC design and test lab! This lab was founded by Professor Kwang-Ting (Tim) Cheng in 1993. We focus on developing methodologies, algorithms, techniques, and tools for validating, verifying, testing, and synthesizing deep sub-micron (DSM) system-on-chip (SoC) devices as well as flexible electronics.

News and Announcements

ITC 2011 Best Student Paper Award

Congratulations to Saeed and Amirali for winning the best student paper award for their paper "End-to-end error correction and online diagnosis for on-chip networks" in International Test Conference 2011.

Posted: Thursday, September 20, 2012 - 14:02

DAC Workshop on More Than Moore Technologies

Peter and Yan presented our recent work in on-chip optical interconnect at the Design Automation Conference workshop on More Than Moore Technologies in San Francisco.

Posted: Friday, June 8, 2012 - 11:23

Peter Lisherness's Ph.D. Defense

Congratulations to Peter on defending his Ph.D. thesis: "Improving Validation Coverage Metrics to Account for Limited Observability".

Posted: Friday, June 8, 2012 - 10:47

Ming Gao's Ph.D. Defense

Congratulations to Ming on defending his Ph.D. thesis: "Cost Effective Error Detection for SoC Validation and Online Testing".

Posted: Tuesday, May 1, 2012 - 17:07

VTS 2012

Amirali will be at the VLSI Test Symposium in Maui to present our recent work in defect diagnosis in NoC.

Posted: Tuesday, April 17, 2012 - 16:46

DATE 2012

Our visiting scholar Yan Zheng will be at DATE in Dresden to present our recent work in on-chip optical communications.

Posted: Friday, March 9, 2012 - 17:27

ASP-DAC 2012

Prof. Cheng and Peter will be at the Asia and South Pacific Design Automation Conference (ASP-DAC) in Sydney to present one invited and two regular papers.

Improving Validation Coverage Metrics to Account for Limited Observability
Post-Fabrication Reconfiguration for Power-Optimized Tuning of Optically Connected Multi-Core Systems
On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation

Posted: Monday, January 23, 2012 - 15:55

GSRC Annual Review

Prof. Cheng, Ming, and Amirali will present research updates at the GSRC annual review November 16-17, 2011.

Posted: Monday, November 7, 2011 - 11:54

HLDVT 2011

Peter will present "Coverage Discounting: A Generalized Approach for Testbench Qualification" at HLDVT'11 on Thursday, November 10th.

Posted: Monday, November 7, 2011 - 11:52

New Site

Our new website is live!

Posted: Monday, October 3, 2011 - 09:06

Recent Publications

Towards Data Reliable Crossbar-Based Memristive Memories

Ghofrani, A., M. Lastras, and K-T. Cheng, "Towards Data Reliable Crossbar-Based Memristive Memories", International Test Conference (ITC), Anaheim, IEEE, 09/2013.

Test Data Analytics - Exploring Spatial and Test-Item Correlations in Production Test Data

Hsu, C-K., F. Lin, K-T. Cheng, W. Zhang, X. Li, J C. M. Jr., and K. M. Butler, "Test Data Analytics - Exploring Spatial and Test-Item Correlations in Production Test Data", International Test Conference (ITC), Anaheim, IEEE, 09/2013.

Mutation Analysis with Coverage Discounting

Lisherness, P., N. Lesperance, and K-T. Cheng, "Mutation Analysis with Coverage Discounting", Design, Automation Test in Europe Conference Exhibition (DATE), 2013, 03/2013.

DATE13.pdf

Power-Efficient Calibration and Reconfiguration for Optical Network-on-Chip

Zheng, Y., P. Lisherness, M. Gao, J. Bovington, K-T. Cheng, H. Wang, and S. Yang, "Power-Efficient Calibration and Reconfiguration for Optical Network-on-Chip", Journal of Optical Communications and Networking, vol. 4, issue 12, 12/2012.

JOCN_FinalResubmit_Yan.pdf

Adaptive Test Selection for Post-Silicon Timing Validation: A Data Mining Approach

Gao, M., P. Lisherness, and K-T(T). Cheng, "Adaptive Test Selection for Post-Silicon Timing Validation: A Data Mining Approach", IEEE 43rd International Test Conference (ITC), Anaheim, California, U. S. A., IEEE, 11/2012.

ITC2012_AdaptiveTestSelection.pdf

A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers

Chang, H-M(S)., J-L. Huang, D-M. Kwai, K-T. Cheng, and C-W. Wu, "A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 04/2012.

Comprehensive Online Defect Diagnosis in On-Chip Networks

Ghofrani, A., R. Parikh, S. Shamshiri, A. DeOrio, K-T(T). Cheng, and V. Bertacco, "Comprehensive Online Defect Diagnosis in On-Chip Networks", VLSI Test Symposium, 04/2012.

VTS12_SRC.pdf

Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication

Zheng, Y., P. Lisherness, M. Gao, J. Bovington, S. Yang, and K-T(T). Cheng, "Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication", DATE'12: Design Automation and Test Europe, 03/2012.

DATE2012_Optical.pdf

Main menu