Biblio

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H. - M. Sherman Chang and Cheng, K. - T. Tim, Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers, in Proceedings of the 48th Design Automation Conference, 2011.
H. - M. Sherman Chang, Cheng, K. - T. Tim, Zhang, W., Li, X., and Butler, K. M., Test cost reduction through performance prediction using virtual probe, in Test Conference (ITC), 2011 IEEE International, 2011.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study, Journal of Electronic Testing, vol. 26, pp. 59-71, 2010.
H. - M. Sherman Chang, Huang, J. - L., Kwai, D. - M., Cheng, K. - T. Tim, and Wu, C. - W., An Error Tolerance Scheme for 3D CMOS Imagers, in Proceedings of the 47th Design Automation Conference, New York, NY, USA, 2010.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, Calibration as a Functional Test: An ADC Case Study, in 2009 Asian Test Symposium, 2009.
H. - M. Sherman Chang and Cheng, K. - T. Tim, TAC: Testing time reduction for digitally-calibrated designs, in Mixed-Signals, Sensors, and Systems Test Workshop, 2009. IMS3TW'09. IEEE 15th International, 2009.
H. - M. Sherman Chang, Chen, C. - H., Lin, K. - Y., and Cheng, K. - T. Tim, Calibration and testing time reduction techniques for a digitally-calibrated pipelined ADC, in VLSI Test Symposium, 2009. VTS'09. 27th IEEE, 2009.
H. - M. Sherman Chang, Lin, K. - Y., Chen, C. - H., and Cheng, K. - T. Tim, A built-in self-calibration scheme for pipelined ADCs, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009.
H. - M. Sherman Chang, Lin, M. - S., and Cheng, K. - T. Tim, Digitally-assisted analog/RF testing for mixed-signal SoCs, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.