Biblio

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Author [ Year(Desc)]
Filters: Author is Hong, Dongwoo  [Clear All Filters]
2006
D. Hong and Cheng, K. - T. Tim, Bit error rate estimation for improving jitter testing of high-speed serial links, in Test Conference, 2006. ITC'06. IEEE International, 2006.
D. Hong, Ong, C. - K., and Cheng, K. - T. Tim, Bit-error-rate estimation for high-speed serial links, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 53, pp. 2616–2627, 2006.
2008
D. Hong and Cheng, K. - T. Tim, Accurate Bit-Error-Rate estimation for efficient high speed I/O testing, in Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on, 2008.
D. Hong and Cheng, K. - T. Tim, Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links, in VLSI Test Symposium, 2008. VTS 2008. 26th IEEE, 2008.
C. - K. Ong, Hong, D., Cheng, K. - T. Tim, and Wang, L. - C., A clock-less jitter spectral analysis technique, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 55, pp. 2263–2272, 2008.
2010
D. Hong and Cheng, K. - T. Tim, A two-tone test method for continuous-time adaptive equalizers, in Efficient Test Methodologies for High-Speed Serial Links, Springer, 2010, pp. 75–87.