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Author
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Abbas, Mohamed
Adam, Gina
Alibart, Fabian
Asada, Kunihiro
Avidan, Shai
Bao, Zhenan
Beausoleil, Raymond G.
Ben Yoo, S.J.
Benini, Luca
Bertacco, Valeria
Bhunia, Swarup
Bovington, Jock
Bowers, John E
Brewer, Forrest
Busetto, Alberto Giovanni
Butler, K.M.
Butler, Kenneth M
Carulli, John
Carulli, J.M.
Chakrabarti, Bhaswar
Chakradhar, Srimat T
Chakradhar, Srimat
Chang, Hsiu-Ming Chang
Chang, Hsiu-Ming Sherman
Chang, Hsiu-Ming Sherman
Chang, Yao-Wen
Chao, Mango C-T
Chao, MC-T
Chen, Jason
Chen, Chin-Hsuan
Chen, Ji-Jan
Chen, Kuang-Chien
Chen, Li
Chen, Chin-Hui
Cheng, Kwang-Ting Tim
Cheng, Kwang-Ting Tim
Chiang, Cheng-Yi
Chu, Ta-Ya
DeOrio, Andrew
Dey, Sujit
Fang, Guanhua
Fedeli, Jean-Marc
Feng, Tao
Feng, Shaoqi
Fern, Nicole
Fiorentino, Marco
Fournier, Maryse
Fukuda, Kenjiro
Furukawa, Yasuo
Gaba, Siddharth
Gao, Ligang
Gao, Ming
Gao, Ming
Ghofrani, Amirali
Guan, Binbin
Guo, Xinjie
Gupta, Rajesh K.
Han, Yinhe
Hanna, Ziyad
Hong, Dongwoo
Hoskins, Brian
Hoskins, Brian D.
Hou, Johnson
Hsu, Chun-Kai
Hsu, Jimmy
Huang, Jiun-Lang
Huang, Tsung-Ching Jim
Huang, Jiun-Lang
Hulme, Jared
Ikeda, Masaaki
Iyer, Madhu K
Klauk, Hagen
Koc, Cetin Kaya
Komatsu, Satoshi
Krstic, Angela
Kulkarni, Shrikant
Kundu, Sandip
Kung, Chen-Pang
Kuribara, Kazunori
Kuwabara, Hirokazu
Kwai, Ding-Ming
Lai, Wei-Cheng
Lan, Fan
Lastras-Montano, Miguel Angel
Lei, Ting
Leisenberger, Friedrich
Lesperance, Nicole
Li, Sicheng
Li, Xin
Li, Huawei
Li, Xin
Li, Cheng
Li, Xiaowei
Lin, Kuan-Yu
Lin, Fan
Lin, Kuan-Yu
Lin, Min-Sheng
Lin, Mitchell
Lin, Yung-Chieh
Lin, Chih-Chang Andy
Liou, Jing-Jia
Lisherness, Peter
Liu, Wei-Ting
Lo, Chun-Ming
Lu, Shelton
Lu, Wei
Lu, Feng
Madhavan, Advait
Mak, TM
Merrikh-Bayat, Farnoud
Mirzaeian, Saeed
Mishra, Prabhat
Moondanos, John
Ong, Chee-Kian
Palermo, Samuel
Pan, Sung-Jui
Pan, Yun
Pan, Yun
Parikh, Ritesh
Parthasarathy, Ganapathy
Payand, Melika
Payvand, Melika
Pitner, Gregoty
Prezioso, Mirko
Rahimi, Abbas
Rofeh, Justin
Roy, Kaushik
Sakurai, Takayasu
San, Ismail
Sarson, Peter
Schatzberger, Gregor
Schow, Clint L.
Sekitani, Tsuyoshi
Seyedi, Ashkan
Shamshiri, Saeed
Shang, Kuanping
Shao, Leilai
Siddhartha, Siddhartha
Sivapurapu, Sridhar
Sodhi, Avantika
Someya, Takao
Someya, Takao
Stanton, Eric J.
Strukov, Dmitri
Strukov, Dmitri B
Strukov, Dmitri B.
Sui, Wenjie
Sun, MC
Swaminathan, Madhavan
Swaminathan, Madhvan
Takimiya, Kazuo
Tao, Ye
Tehranipoor, Mark
Theogarajan, Luke
Tseng, Huai-Yuan
Wang, Seongmoon
Wang, Ping-Ying
Wang, Yuyang
Wang, Li-C
Wang, Li C
Wang, Hong
Wang, Laung-Terng
Wang, Hong
Wei, Wen-Long
Wei, Wenlong
Wen, CH-P
Wong, Man
Wong, H.-S. Philip
Wu, Yi-Leh
Wu, Cheng-Wen
Wu, Rui
Wu, Ching-Tung
Xiang, Dong
Xiang, Dong
Xu, Dawen
Yamamoto, Tatsuya
Yan, Xiaolang
Yang, Shiyuan
Yang, Kai
Yeh, Mei-Chen
Yeh, Yung-Hui
Yemenicioglu, Sukru
Yin, Boxue
Yin, Boxue
Yokota, Tomoyuki
Zhang, Wangyang
Zhang, Zeyu
Zhang, Wangyang
Zhang, Chong
Zhang, Shuangyue
Zhang, Chong
Zhang, Ling
Zheng, Yan
Zheng, Yuqing
Zheng, Feijun
Zhong, Yizhou
Zhu, Qiang
Zhu, Chenxin
Zschieschang, Ute
Type
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Conference Paper
Journal Article
Conference Proceedings
Book Chapter
Miscellaneous
Book
Term
any
Year
any
2019
2018
2017
2016
2015
2014
2013
2012
2011
2010
2009
2008
2007
2006
2005
2002
Keyword
any
$n$ -detection test
1-n detection
12-bit memories
16-bit memories
24-bit memories
3D IC
3D integrated design
8-bit memories
accelerated fault simulation
Access-Transistor-Free
Accuracy
Adaptive Write Scheme
ADC
ADC testing
AES design
all-digital built-in self-test
all-digital built-in self-test technique
AMM module
analog-to-digital conversion
analog-to-digital converters
analogue-digital conversion
analysis
Application specific integrated circuits
application-aware testing
application-specific profile feedback
Approximate computing
approximate longest sensitized path metric
Arrays
ASIC implementation
Assertion checker
associative memory
associative memristive memory module
asymmetric voltages
at-speed testing
ATF memristive crossbar scalability
athermal characteristics
athermal waveguide design
automated diagnosis
automatic test pattern generation
automatic test pattern generation circuit model
automatic test pattern generation tool
bang-bang phase-frequency detector
BCH codes
Benchmark testing
BIST
built-in postfabrication tunability
built-in self test
Built-in self-test
C models
C++ language
C++ models
calibration
calibration circuitry
canonical analysis
chip area overhead reduction
chip test measurement
CHStone C high-level-synthesis benchmark set
Circuit faults
Circuit optimization
circuit reliability
Circuit simulation
Circuit testing
circuit yield
Clocks
CMOS integrated circuits
CMOS technology
Collaboration
collaborative compilation
Communication channels
compact test generation
Compaction
compiler
complex chips
Computer architecture
Computer bugs
Computer industry
conflict avoidance
controllability metrics
Correlation
correlation exploration
cost
cost reduction
cost-sensitive electronic products
costing
Costs
coverage
coverage metrics
Crossbar
crossbar-based memristor arrays
cryptographic hardware
cryptography
DAC
Data analysis
data reliability
data reliability problems
data reliable crossbar-based memristive memories
Debugging
decoding
defect screening
Delay
Delays
Design engineering
design flow
Design for debug
Design for disassembly
Design for testability
design modifications
design style
design-for-debug technique
device characteristics
device under test
DfD technique
die
Digital calibration
Digital circuits
digital signal processing chips
digital-analogue conversion
digital-to-analog conversion
digitally-assisted analog circuits
Digitally-assisted testing
digitally-calibrated ADC
Discrete cosine transforms
disturbance confinement
disturbance detection
dynamic power overhead reduction
dynamic test compaction
effective-number of bits
efficient silicon characterization
eFPGA core
Electrical products industry
electron probes
Electronic equipment testing
electronic systems
elemental semiconductors
embedded field programmable gate array
embedded FPGA
embedded FPGA block
energy conservation
energy consumption
Energy efficiency
energy saving
energy use
energy-efficiency techniques
energy-efficient GPGPU architecture
equalization-based calibration scheme
Equations
error correction
error correction codes
error detection
error injection tools
error tolerance
error transfer function
error-locality-aware codes
error-locality-aware linear coding
Estimation
exhaustive testing
fault coverage
Fault detection
fault diagnosis
fault simulation
faulty design module
faulty timing behavior
feature engineering
Feature extraction
feature transformation
field programmable gate arrays
flexible electronic design style
flexible electronics
Flexible printed circuits
floating point units
floating point units (FPUs)
FPU
Frequency modulation
frequency modulator
frequency synthesizer
GCC compiler
General public utilities (GPU)
general public utility
general purpose graphics processing unit
Genetic mutations
Glass
global error
Golay codes
GPGPUs
GPU architecture parallelism
GPU-based fault simulator
graphics processing units
graphics processing units (GPUs)
H.264 decoder
hard-to-detect bug
Hardware
High level synthesis
high-level synthesis
high-volume industrial device
Hopfield neural nets
Hopfield neural network
Hopfield neural network circuit
Hopfield neural networks
hybrid circuit
hybrid circuits
image sensor
in-field failure
in-field failure rates
in-field testing
Indexes
indium compounds
industrial products
InGaZnO
injected error detection
inner links
integrated circuit design
Integrated circuit measurements
Integrated circuit modeling
integrated circuit reliability
Integrated circuit synthesis
integrated circuit testing
integrated circuit yield
integrated memory circuits
integrated optics
inter-test-item correlations
interface routing
intertest item correlations
intertest-item correlations
Inverters
joint exploration
joint virtual probe
Joints
JVP implicit use
k-bit subspaces
Kernel
kernel execution
large-scale access-transistor-free memristive crossbar
launch-on-capture (LOC) delay testing
launch-on-capture scan testing
launch-on-capture transition fault testing
Leakage currents
Leakage-Current Filtering
Least-mean-squared (LMS) adaptation algorithm
life time resiliency
linear codes
Logic devices
Logic gates
logic testing
longest sensitized path
low computational complexity
low overhead time-multiplexed online checking
low-cost electronics
low-cost resilience
low-cost substrate
low-power
low-power electronics
low-power memory
malicious circuitry
Manuals
Manufacturing
manufacturing defect
Manufacturing processes
manufacturing test
manufacturing testing
March Algorithm
Mathematical model
measurement values
memory access
Memory Testing
memory usage optimization
memory-based computing
Memristive Crossbar
memristive memory-based computing
memristor
memristor circuits
memristors
mesh based NoC
metal oxide memristors
microarchitectural design
microprocessor chips
mixed analogue-digital integrated circuits
mixed-signal circuit
Mixed-signal testing
mono type thin film transistors
multibit upsets
Multicore processing
multiple test items
mutation
mutation injection tool
n-detection fault simulation
n-detection test
Nanoscale devices
Nanowires
network analysis
Network-on-a-chip
network-on-chip
Neurons
nGFSIM
NoC
Noise
non-uniform spare distributtion
Nonvolatile
numerical analysis
numerical simulation
Observability
observability metrics
offset errors
on-chip reconfigurable block
on-chip stimulus synthesis
Online ResistanceMonitoring
online testing
op-amp
operational amplifier
optical design techniques
optical resonators
Optical ring resonators
Optical waveguides
organic semiconductors
organic TFT
Organic thin film transistors
OSCI SystemC example models
outer links
parallel architectures
parallel test selection method
parametric test items
parasitic effect
partially-selected device
Partitioning algorithms
per-cell access-transistor
Permission
Phase frequency detector
phase locked loops
physical defects
physical measurement
Pipelines
plaintext bits
Plastics
platinum
PLL
PLL architectures
plugin interface
post fabrication tuning
post-silicon bug detection
post-silicon bug isolation
post-silicon debugging
post-silicon hardware trojan detection
Post-silicon validation
power aware computing
Predictive models
Principal component analysis
Production
production engineering
production test data
production test programs
production test strategy
production testing
program compilers
program diagnostics
program verification
Programmable logic arrays
Protocols
pseudo CMOS
pseudo-CMOS
Pt-TiO2-x-Pt
quality analysis
quality assurance
quality assurance technique
quality constraint
quality metric
Radio frequency
radiofrequency integrated circuits
random-access storage
Redundancy
Registers
regression analysis
reliability
reliability simulation
ReRAM
Research and development
Resistance
resistive switching devices
resonance shift
response analysis
RF circuit
RFID tags
ring resonance wavelengths
ring resonators
robust circuit/system design
robust flexible electronics
Robustness
Runtime
runtime reduction
SAT-solver
SCEMIT
screen potential test escape
second-order effects
second-order thermo-optical effects
security
Semiconductor device measurement
Semiconductor device modeling
semiconductor technology
Sensitivity
Sensors
sequential backtracing scheme
Si
sigma-delta fractional-N RF PLLs
Silicon
silicon debugging
Silicon photonics
silicon substrate
single-bit upset
single-run fault simulation
small delay defect
SoC
Sociology
Software algorithms
software metrics
spare programmable core
spare wires
spare-enhanced multi-core chip subject
spatial correlations
spatial item correlations
spatial pattern
spatial patterns
spatial variations
spatiotemporal reuse
spectral dependency
SRAM
SRAM chips
SRAM memory
standard cell
static gain
statistical analysis
statistical regression method
statistical regression tools
statistical test
statistical testing
steady-state fluctuation
storage management chips
Stress
stuck-at faults
Substrates
Switches
syndrome analysis
System analysis and design
System recovery
System testing
system-on-chip
SystemC
SystemC error
Telecommunication network reliability
temperature 20 degC to 50 degC
Temperature measurement
temporal correlations
ternary content-addressable memory (TCAM)
test circuitry
test cost reduction
test data analytics
test data compression
test prediction
test program
test quality improvement
test quality optimization
test response compaction
test response compaction.
test selection
test time reduction
Testing
TFT technology
TFT-LCD displays
Thermal degradation
thermal stress
thermal stresses
thermo-optical effects
thermo-stress-optic behavior
thin film circuits
thin film transistor
thin film transistors
three-dimensional integrated circuits
time division multiplexing
time-multiplexed
time-multiplexed assertion checking
Timing
timing aware test selection method
timing errors
timing sensitivity
TiO2-clad silicon waveguides
TiO2-Si
titanium compounds
TMAC implementation
TMOC checker
Topology
Training
transfer function characterization
transfer functions
Transistors
transition fault (TF)
transition fault (TF).
transition fault detection
triple-error-correcting Golay code
Trojan horses
TV
ultra-low power computing
ultradense memory system
ultrahigh-density
Variation-Aware Design
variations
Vectors
verification effort
Very large scale integration
video coding
virtual probe
Voltage measurement
voltage overscaling
wafer
wavelength 1.3 mum
Wavelength measurement
weighted group lasso
weighted optimization problem
Wires
word length 4 bit
word length 6 bit
yield and cost modeling
yield enhancement
Export 1 results:
BibTeX
Author
[
Year
]
Filters:
Author
is
Chen, Kuang-Chien
[Clear All Filters]
2005
F. Lu
,
Iyer, M. K.
,
Parthasarathy, G.
,
Wang, L. - C.
,
Cheng, K. - T. Tim
, and
Chen, K. - C.
,
“
An efficient sequential SAT solver with improved search strategies
”
, in
Proceedings of the conference on Design, Automation and Test in Europe-Volume 2
, 2005, pp. 1102–1107.
Google Scholar
BibTeX
]