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C. - K. Ong, Hong, D., Cheng, K. - T. Tim, and Wang, L. - C., A clock-less jitter spectral analysis technique, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 55, pp. 2263–2272, 2008.
F. Lu, Iyer, M. K., Parthasarathy, G., Wang, L. - C., Cheng, K. - T. Tim, and Chen, K. - C., An efficient sequential SAT solver with improved search strategies, in Proceedings of the conference on Design, Automation and Test in Europe-Volume 2, 2005, pp. 1102–1107.
C. H. - P. Wen, Wang, L. - C., Cheng, K. - T. Tim, Yang, K., Liu, W. - T., Chen, J. - J., and , On a software-based self-test methodology and its application, in VLSI Test Symposium, 2005. Proceedings. 23rd IEEE, 2005, pp. 107–113.
K. Yang, Wang, L. - C., Cheng, K. - T. Tim, and Kundu, S., On statistical correlation based path selection for timing validation, in VLSI Design, Automation and Test, 2005.(VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on, 2005, pp. 8–11.
T. Feng, Wang, L. - C., Cheng, K. - T. Tim, and Lin, C. - C. Andy, Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 10, pp. 627–650, 2005.