Biblio

Export 152 results:
Author [ Year(Asc)]
2012
K. - T. Tim Cheng and Strukov, D. B., 3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications, in Proceedings of the 2012 ACM International Symposium on Physical Design, 2012.
M. Gao, Lisherness, P., and Cheng, K. - T. Tim, Adaptive test selection for post-silicon timing validation: A data mining approach, in Test Conference (ITC), 2012 IEEE International, 2012.
A. Ghofrani, Parikh, R., Shamshiri, S., DeOrio, A., Cheng, K. - T. Tim, and Bertacco, V., Comprehensive online defect diagnosis in on-chip networks., in VLSI Test Symposium (VTS), 2012. VTS12_cr.pdf (710.92 KB)
M. Gao, Lisherness, P., Cheng, K. - T. Tim, and Liou, J. - J., On error modeling of electrical bugs for post-silicon timing validation, in Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 2012.
P. Lisherness and Cheng, K. - T. Tim, Improving validation coverage metrics to account for limited observability, in Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 2012.
Y. Zheng, Lisherness, P., Shamshiri, S., Ghofrani, A., Yang, S., and Cheng, K. - T. Tim, Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems, in Design Automation Conference (ASP-DAC), Asia and South Pacific, 2012. ASPDAC2012_optical.pdf (221.18 KB)
Y. Zheng, Lisherness, P., Gao, M., Bovington, J., Yang, S., and Cheng, K. - T. Tim, Power-efficient calibration and reconfiguration for on-chip optical communication, in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012. DATE2012_optical.pdf (341.67 KB)
Y. Zheng, Lisherness, P., Gao, M., Bovington, J., Cheng, K. - T., Wang, H., and Yang, S., Power-efficient calibration and reconfiguration for optical network-on-chip, Journal of Optical Communications and Networking, vol. 4, pp. 955–966, 2012. JOCN2012.pdf (1.49 MB)
2011
P. - Y. Wang, Chang, H. - M. Sherman, and Cheng, K. - T. Tim, An all-digital built-in self-test technique for transfer function characterization of RF PLLs, in Design, Automation Test in Europe Conference Exhibition (DATE), 2011, 2011.
P. Lisherness and Cheng, K. - T. Tim, Coverage discounting: A generalized approach for testbench qualification, in High Level Design Validation and Test Workshop (HLDVT), 2011 IEEE International, 2011.
S. Shamshiri, Ghofrani, A., and Cheng, K. - T. Tim, End-to-end error correction and online diagnosis for on-chip networks, in Test Conference (ITC), 2011 IEEE International, 2011. ITC11.pdf (502.59 KB)
H. - M. Sherman Chang and Cheng, K. - T. Tim, Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers, in Proceedings of the 48th Design Automation Conference, 2011.
S. Shamshiri and Cheng, K. - T. Tim, Modeling yield, cost, and quality of a spare-enhanced multicore chip, Computers, IEEE Transactions on, vol. 60, pp. 1246–1259, 2011.
K. Fukuda, Sekitani, T., Yokota, T., Kuribara, K., Huang, T. - C., Sakurai, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic pseudo-CMOS circuits for low-voltage large-gain high-speed operation, Electron Device Letters, IEEE, vol. 32, pp. 1448–1450, 2011.
K. Fukuda, Huang, T. - C., Kuribara, K., Yokota, T., Sekitani, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic Pseudo-CMOS for 2V Operational High-Speed Circuits. 2011.
M. Gao, Lisherness, P., and Cheng, K. - T. Tim, Post-silicon Bug Detection for Variation Induced Electrical Bugs, in Proceedings of the 16th Asia and South Pacific Design Automation Conference, Piscataway, NJ, USA, 2011.
T. - C. Huang, Fukuda, K., Lo, C. - M., Yeh, Y. - H., Sekitani, T., Someya, T., and Cheng, K. - T. Tim, Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics, Electron Devices, IEEE Transactions on, vol. 58, pp. 141-150, 2011.
T. - C. Huang, Huang, J. - L., and Cheng, K. - T. Tim, Robust circuit design for flexible electronics, IEEE Design and Test of Computers, vol. 28, pp. 8–15, 2011.
H. - M. Sherman Chang, Cheng, K. - T. Tim, Zhang, W., Li, X., and Butler, K. M., Test cost reduction through performance prediction using virtual probe, in Test Conference (ITC), 2011 IEEE International, 2011.
M. Gao, Chang, H. - M. Sherman, Lisherness, P., and Cheng, K. - T. Tim, Time-multiplexed online checking, Computers, IEEE Transactions on, vol. 60, pp. 1300–1312, 2011.

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