Biblio

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B. Chakrabarti, Lastras-Montano, M. Angel, Adam, G., Prezioso, M., Hoskins, B., Cheng, K. - T. Tim, and Strukov, D. B., “A Multiply-Add Engine with Monolithically Integrated 3D Memristor Crossbar/CMOS Hybrid Circuit”, Nature Scientific Reports, 2017.
H. - M. Sherman Chang, Lin, M. - S., and Cheng, K. - T. Tim, “Digitally-assisted analog/RF testing for mixed-signal SoCs”, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.
H. - M. Sherman Chang and Cheng, K. - T. Tim, “Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers”, in Proceedings of the 48th Design Automation Conference, 2011.
H. - M. Sherman Chang, Cheng, K. - T. Tim, Zhang, W., Li, X., and Butler, K. M., “Test cost reduction through performance prediction using virtual probe”, in Test Conference (ITC), 2011 IEEE International, 2011.
H. - M. Chang Chang, Huang, J. - L., Kwai, D. - M., Cheng, K. - T. Tim, and Wu, C. - W., “Low-cost error tolerance scheme for 3-D CMOS imagers”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 21, pp. 465–474, 2013.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, “Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study”, Journal of Electronic Testing, vol. 26, pp. 59-71, 2010.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, “Calibration-assisted production testing for digitally-calibrated ADCs”, in VLSI Test Symposium (VTS), 2010 28th, 2010.
H. - M. Sherman Chang, Huang, J. - L., Kwai, D. - M., Cheng, K. - T. Tim, and Wu, C. - W., “An Error Tolerance Scheme for 3D CMOS Imagers”, in Proceedings of the 47th Design Automation Conference, New York, NY, USA, 2010.
H. - M. Sherman Chang and Cheng, K. - T. Tim, “Low-cost quality assurance techniques for high-performance mixed-signal/RF circuits and systems”, in Test Conference (ITC), 2010 IEEE International, 2010.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, “Calibration as a Functional Test: An ADC Case Study”, in 2009 Asian Test Symposium, 2009.
H. - M. Sherman Chang and Cheng, K. - T. Tim, “TAC: Testing time reduction for digitally-calibrated designs”, in Mixed-Signals, Sensors, and Systems Test Workshop, 2009. IMS3TW'09. IEEE 15th International, 2009.
H. - M. Sherman Chang, Chen, C. - H., Lin, K. - Y., and Cheng, K. - T. Tim, “Calibration and testing time reduction techniques for a digitally-calibrated pipelined ADC”, in VLSI Test Symposium, 2009. VTS'09. 27th IEEE, 2009.
H. - M. Sherman Chang, Lin, K. - Y., Chen, C. - H., and Cheng, K. - T. Tim, “A built-in self-calibration scheme for pipelined ADCs”, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009.
M. C. - T. Chao, Wang, S., Chakradhar, S. T., and Cheng, K. - T. Tim, “ChiYun compact: a novel test compaction technique for responses with unknown values”, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 147–152.
M. C. - T. Chao, Wang, S., Chakradhar, S. T., and Cheng, K. - T. Tim, “Response shaper: a novel technique to enhance unknown tolerance for output response compaction”, in Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on, 2005, pp. 80–87.
M. C. - T. Chao, Wang, S., Chakradhar, S. T., Wei, W., and Cheng, K. - T. Tim, “Coverage loss by using space compactors in presence of unknown values”, in Proceedings of the conference on Design, automation and test in Europe: Proceedings, 2006, pp. 1053–1054.
M. C. - T. Chao, Cheng, K. - T. Tim, Wang, S., Chakradhar, S., and Wei, W. - L., “Unknown-tolerance analysis and test-quality control for test response compaction using space compactors”, in Proceedings of the 43rd annual Design Automation Conference, 2006.
M. C. - T. Chao, Cheng, K. - T. Tim, Wang, S., Chakradhar, S. T., and Wei, W. - L., “A hybrid scheme for compacting test responses with unknown values”, in Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007.
K. - T. Tim Cheng and Strukov, D. B., “3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications”, in Proceedings of the 2012 ACM International Symposium on Physical Design, 2012.
K. - T. Tim Cheng and Chang, H. - M. Sherman, “Recent Advances in Analog, Mixed-Signal, and RF Testing”, Information and Media Technologies, vol. 5, pp. 338-365, 2010.
K. - T. Tim Cheng and Huang, T. - C. Jim, “Design, analysis, and test of low-power and reliable flexible electronics”, in VLSI Test Symposium (VTS), 2010 28th, 2010.
K. - T. Tim Cheng, “Embedded Software-Based Self-Testing for SoC Design”, in Embedded Systems Handbook, CRC Press, 2005, pp. 28-1-28-19.
K. - T. Tim Cheng, “Automatic Test Pattern Generation”, in EDA for IC System Design, Verification, and Testing, CRC Press, 2006.
K. - T. Tim Cheng and Chang, H. - M. Sherman, “Test strategies for adaptive equalizers”, in Custom Integrated Circuits Conference, 2009. CICC'09. IEEE, 2009.