Biblio

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2007
M. C. - T. Chao, Cheng, K. - T. Tim, Wang, S., Chakradhar, S. T., and Wei, W. - L., A hybrid scheme for compacting test responses with unknown values, in Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007.
M. C. - T. Chao, Cheng, K. - T. Tim, Wang, S., Chakradhar, S. T., and Wei, W. - L., A hybrid scheme for compacting test responses with unknown values, in Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007.
M. C. - T. Chao, Cheng, K. - T. Tim, Wang, S., Chakradhar, S. T., and Wei, W. - L., A hybrid scheme for compacting test responses with unknown values, in Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007.
Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Multiple-fault diagnosis based on adaptive diagnostic test pattern generation, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 932–942, 2007.
K. Yang and Cheng, K. - T. Tim, Silicon Debug for Timing Errors, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 2084–2088, 2007.
M. Lin and Cheng, K. - T. Tim, Testable design for advanced serial-link transceivers, in Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE'07, 2007.
2008
D. Hong and Cheng, K. - T. Tim, Accurate Bit-Error-Rate estimation for efficient high speed I/O testing, in Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on, 2008.
D. Hong and Cheng, K. - T. Tim, Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links, in VLSI Test Symposium, 2008. VTS 2008. 26th IEEE, 2008.
C. - K. Ong, Hong, D., Cheng, K. - T. Tim, and Wang, L. - C., A clock-less jitter spectral analysis technique, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 55, pp. 2263–2272, 2008.
S. Shamshiri, Lisherness, P., Pan, S. - J., and Cheng, K. - T. Tim, A cost analysis framework for multi-core systems with spares, in Test Conference, 2008. ITC 2008. IEEE International, 2008.
H. - M. Sherman Chang, Lin, M. - S., and Cheng, K. - T. Tim, Digitally-assisted analog/RF testing for mixed-signal SoCs, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.
H. - M. Sherman Chang, Lin, M. - S., and Cheng, K. - T. Tim, Digitally-assisted analog/RF testing for mixed-signal SoCs, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.
T. - C. Jim Huang, Cheng, K. - T. Tim, Tseng, H. - Y., and Kung, C. - P., Reliability analysis for flexible electronics: Case study of integrated a-Si: H TFT scan driver, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 4, no. 3, 2008.
S. Mirzaeian, Zheng, F., and Cheng, K. - T. Tim, RTL error diagnosis using a word-level SAT-solver, in Test Conference, 2008. ITC 2008. IEEE International, 2008.
M. Gao, Chang, H. - M. Sherman, Lisherness, P., and Cheng, K. - T. Tim, Time-Multiplexed Online Checking: A Feasibility Study, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.
M. Gao, Chang, H. - M. Sherman, Lisherness, P., and Cheng, K. - T. Tim, Time-Multiplexed Online Checking: A Feasibility Study, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.
2009
H. - M. Sherman Chang, Lin, K. - Y., Chen, C. - H., and Cheng, K. - T. Tim, A built-in self-calibration scheme for pipelined ADCs, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009.
H. - M. Sherman Chang, Lin, K. - Y., Chen, C. - H., and Cheng, K. - T. Tim, A built-in self-calibration scheme for pipelined ADCs, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009.
H. - M. Sherman Chang, Lin, K. - Y., Chen, C. - H., and Cheng, K. - T. Tim, A built-in self-calibration scheme for pipelined ADCs, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009.
H. - M. Sherman Chang, Chen, C. - H., Lin, K. - Y., and Cheng, K. - T. Tim, Calibration and testing time reduction techniques for a digitally-calibrated pipelined ADC, in VLSI Test Symposium, 2009. VTS'09. 27th IEEE, 2009.
H. - M. Sherman Chang, Chen, C. - H., Lin, K. - Y., and Cheng, K. - T. Tim, Calibration and testing time reduction techniques for a digitally-calibrated pipelined ADC, in VLSI Test Symposium, 2009. VTS'09. 27th IEEE, 2009.
H. - M. Sherman Chang, Chen, C. - H., Lin, K. - Y., and Cheng, K. - T. Tim, Calibration and testing time reduction techniques for a digitally-calibrated pipelined ADC, in VLSI Test Symposium, 2009. VTS'09. 27th IEEE, 2009.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, Calibration as a Functional Test: An ADC Case Study, in 2009 Asian Test Symposium, 2009.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, Calibration as a Functional Test: An ADC Case Study, in 2009 Asian Test Symposium, 2009.
T. - C. Jim Huang and Cheng, K. - T. Tim, Design for low power and reliable flexible electronics: Self-tunable cell-library design, Display Technology, Journal of, vol. 5, pp. 206–215, 2009.

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