Biblio
] , “Constraint extraction for pseudo-functional scan-based delay testing”, in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, 2005, pp. 166–171.
, “An Artificial Neural Network Approach for Screening Test Escapes”, Asia and South Pacific Design Automation Conference (ASP-DAC). Chiba/Tokyo, Japan, 2017.
aspdac17.pdf (810.67 KB)
aspdac17.pdf (810.67 KB), “Testable design for advanced serial-link transceivers”, in Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE'07, 2007.
, “Pseudo-functional scan-based bist for delay fault”, in VLSI Test Symposium, 2005. Proceedings. 23rd IEEE, 2005, pp. 229–234.
, “Multiple-fault diagnosis based on adaptive diagnostic test pattern generation”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 932–942, 2007.
, “Accurate diagnosis of multiple faults”, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 153–156.
, “Production-oriented interface testing for PCI-Express by enhanced loop-back technique”, in Test Conference, 2005. Proceedings. ITC 2005. IEEE International, 2005, p. 10–pp.
, “nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications”, in Test Conference (ITC), 2010 IEEE International, 2010.
, “Hardware Trojan Detection Using Exhaustive Testing of k-bit Subspaces”, in Asia and South Pacific Design Automation Conference (ASP-DAC), 2015. ASPDAC2015.pdf (508.45 KB)
ASPDAC2015.pdf (508.45 KB), “Low-voltage High-performance Flexible Digital and Analog Circuits based on Ultrahigh-purity Semiconducting Carbon Nanotubes”, Nature Communication, 2019. s41467-019-10145-9.pdf (3.65 MB)
s41467-019-10145-9.pdf (3.65 MB), “Architecting Low Power Crossbar-Based Memristive RAM”, in Non-Volatile Memory Workshop, San Diego, USA, 2013. NVMW13.pdf (721.83 KB)
NVMW13.pdf (721.83 KB), “A Low-Power Hybrid Reconfigurable Architecture For Resistive Random-Access Memories”, in International Symposium on High-Performance Computer Architecture (HPCA), Barcelona, Spain, 2016. HPCA16_1.pdf (6.47 MB)
HPCA16_1.pdf (6.47 MB), “HReRAM: A Hybrid Reconfigurable Resistive Random-Access Memory”, Proceedings Design, Automation, and Test in Europe (DATE), IEEE, 2015. DATE15_1.pdf (5.59 MB)
DATE15_1.pdf (5.59 MB), “3D-DPE: A 3D High-Bandwidth Dot-Product Engine for High-Performance Neuromorphic Computing”, Design, Automation and Test in Europe (DATE). Lausanne, Switzerland, 2017.
, “Architecting Energy Efficient Crossbar-based Memristive Random Access Memories”, in ACM/IEEE Internation Symposium on Nano-scale Architectures (NANOARCH'15), 2015. NANOARCH15.pdf (3.42 MB)
NANOARCH15.pdf (3.42 MB), “DLPS: Dynamic Laser Power Scaling for Optical Network-on-Chip”, in Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba/Tokyo, Japan, 2017. laser_final.pdf (2.21 MB)
laser_final.pdf (2.21 MB), “Embedded software-based self-testing for SoC design”, in Proceedings of the 39th annual Design Automation Conference, 2002, pp. 355–360.
, “Efficient conflict-based learning in an RTL circuit constraint solver”, in Design, Automation and Test in Europe, 2005. Proceedings, 2005, pp. 666–671.
, “DWDM Nanophotonic Interconnects: Toward Terabit/s Chip-Scale Serial Link”, in International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, Colorado, 2015. DWDM_nanophotnic link_JimHuang_camera_ready.pdf (1.23 MB)
DWDM_nanophotnic link_JimHuang_camera_ready.pdf (1.23 MB), “Pseudo-CMOS: A novel design style for flexible electronics”, in Design, Automation Test in Europe Conference Exhibition (DATE), 2010, 2010.
, “Robust Design and Design Automation for Flexible Hybrid Electronics”, in International Symposium on Circuits and Systems (ISCAS), 2017.
, “Process Design Kit and Design Automation for Flexible Hybrid Electronics”, in Design Automation And Test in Europe (Invited Paper), Florence, Italy, 2019. DATE19_Jim_submission.pdf (2.4 MB)
DATE19_Jim_submission.pdf (2.4 MB), “Process Design Kit and Design Automation for Flexible Hybrid Electronics”, in SID International Symposium, 2019. (invited paper), 2019. FHEPDK_Jim_Huang_SID19_for_review_v1.pdf (665.97 KB)
FHEPDK_Jim_Huang_SID19_for_review_v1.pdf (665.97 KB), “Design, Automation, and Test for Low-Power and Reliable Flexible Electronics”, Foundations and Trends in Electronic Design Automation, vol. 9, pp. 99-210, 2015.
, “Design for low power and reliable flexible electronics: Self-tunable cell-library design”, Display Technology, Journal of, vol. 5, pp. 206–215, 2009.