Biblio

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Author [ Year(Asc)]
Filters: Author is Lisherness, Peter  [Clear All Filters]
2013
P. Lisherness, Lesperance, N., and Cheng, K. - T. Tim, “Mutation analysis with coverage discounting”, in Design, Automation Test in Europe Conference (DATE), 2013.PDF icon DATE13.pdf (167.64 KB)
2012
M. Gao, Lisherness, P., and Cheng, K. - T. Tim, “Adaptive test selection for post-silicon timing validation: A data mining approach”, in Test Conference (ITC), 2012 IEEE International, 2012.
M. Gao, Lisherness, P., Cheng, K. - T. Tim, and Liou, J. - J., “On error modeling of electrical bugs for post-silicon timing validation”, in Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 2012.
P. Lisherness and Cheng, K. - T. Tim, “Improving validation coverage metrics to account for limited observability”, in Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 2012.
Y. Zheng, Lisherness, P., Shamshiri, S., Ghofrani, A., Yang, S., and Cheng, K. - T. Tim, “Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems”, in Design Automation Conference (ASP-DAC), Asia and South Pacific, 2012.PDF icon ASPDAC2012_optical.pdf (221.18 KB)
Y. Zheng, Lisherness, P., Gao, M., Bovington, J., Yang, S., and Cheng, K. - T. Tim, “Power-efficient calibration and reconfiguration for on-chip optical communication”, in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012.PDF icon DATE2012_optical.pdf (341.67 KB)
Y. Zheng, Lisherness, P., Gao, M., Bovington, J., Cheng, K. - T. Tim, Wang, H., and Yang, S., “Power-efficient calibration and reconfiguration for optical network-on-chip”, Journal of Optical Communications and Networking, vol. 4, pp. 955–966, 2012.PDF icon JOCN2012.pdf (1.49 MB)
2011
P. Lisherness and Cheng, K. - T. Tim, “Coverage discounting: A generalized approach for testbench qualification”, in High Level Design Validation and Test Workshop (HLDVT), 2011 IEEE International, 2011.
M. Gao, Lisherness, P., and Cheng, K. - T. Tim, “Post-silicon Bug Detection for Variation Induced Electrical Bugs”, in Proceedings of the 16th Asia and South Pacific Design Automation Conference, Piscataway, NJ, USA, 2011.
M. Gao, Chang, H. - M. Sherman, Lisherness, P., and Cheng, K. - T. Tim, “Time-multiplexed online checking”, Computers, IEEE Transactions on, vol. 60, pp. 1300–1312, 2011.
2010
P. Lisherness and Cheng, K. - T. Tim, “SCEMIT: A SystemC error and mutation injection tool”, in Design Automation Conference (DAC), 2010 47th ACM/IEEE, 2010.
2009
P. Lisherness and Cheng, K. - T. Tim, “An instrumented observability coverage method for system validation”, in High Level Design Validation and Test Workshop, 2009. HLDVT 2009. IEEE International, 2009.
2008
S. Shamshiri, Lisherness, P., Pan, S. - J., and Cheng, K. - T. Tim, “A cost analysis framework for multi-core systems with spares”, in Test Conference, 2008. ITC 2008. IEEE International, 2008.
M. Gao, Chang, H. - M. Sherman, Lisherness, P., and Cheng, K. - T. Tim, “Time-Multiplexed Online Checking: A Feasibility Study”, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.