Biblio

Export 166 results:
Author [ Year(Asc)]
2010
P. Lisherness and Cheng, K. - T. Tim, SCEMIT: A SystemC error and mutation injection tool, in Design Automation Conference (DAC), 2010 47th ACM/IEEE, 2010.
D. Hong and Cheng, K. - T. Tim, A two-tone test method for continuous-time adaptive equalizers, in Efficient Test Methodologies for High-Speed Serial Links, Springer, 2010, pp. 75–87.
2009
H. - M. Sherman Chang, Lin, K. - Y., Chen, C. - H., and Cheng, K. - T. Tim, A built-in self-calibration scheme for pipelined ADCs, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009.
H. - M. Sherman Chang, Chen, C. - H., Lin, K. - Y., and Cheng, K. - T. Tim, Calibration and testing time reduction techniques for a digitally-calibrated pipelined ADC, in VLSI Test Symposium, 2009. VTS'09. 27th IEEE, 2009.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, Calibration as a Functional Test: An ADC Case Study, in 2009 Asian Test Symposium, 2009.
T. - C. Jim Huang and Cheng, K. - T. Tim, Design for low power and reliable flexible electronics: Self-tunable cell-library design, Display Technology, Journal of, vol. 5, pp. 206–215, 2009.
D. Xiang, Yin, B., and Cheng, K. - T. Tim, Dynamic test compaction for transition faults in broadside scan testing based on an influence cone measure, in VLSI Test Symposium, 2009. VTS'09. 27th IEEE, 2009.
D. Hong and Cheng, K. - T. Tim, Efficient test methodologies for high-speed serial links, vol. 51. Springer Science & Business Media, 2009.
L. - T. Wang, Chang, Y. - W., and Cheng, K. - T. Tim, Electronic design automation: synthesis, verification, and test. Morgan Kaufmann, 2009.
P. Lisherness and Cheng, K. - T. Tim, An instrumented observability coverage method for system validation, in High Level Design Validation and Test Workshop, 2009. HLDVT 2009. IEEE International, 2009.
M. Gao and Cheng, K. - T. Tim, Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder, in Asian Test Symposium, 2009. ATS '09., 2009.
F. Lu and Cheng, K. - T. Tim, SEChecker: A Sequential Equivalence Checking Framework Based on th Invariants, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 17, pp. 733–746, 2009.
M. Abbas, Cheng, K. - T. Tim, Furukawa, Y., Komatsu, S., and Asada, K., Signature-based testing for digitally-assisted adaptive equalizers in high-speed serial links, in Test Symposium, 2009 14th IEEE European, 2009.
H. - M. Sherman Chang and Cheng, K. - T. Tim, TAC: Testing time reduction for digitally-calibrated designs, in Mixed-Signals, Sensors, and Systems Test Workshop, 2009. IMS3TW'09. IEEE 15th International, 2009.
K. - T. Tim Cheng and Chang, H. - M. Sherman, Test strategies for adaptive equalizers, in Custom Integrated Circuits Conference, 2009. CICC'09. IEEE, 2009.
S. Shamshiri and Cheng, K. - T. Tim, Yield and cost analysis of a reliable NoC, in VLSI Test Symposium, 2009. VTS'09. 27th IEEE, 2009.
2008
D. Hong and Cheng, K. - T. Tim, Accurate Bit-Error-Rate estimation for efficient high speed I/O testing, in Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on, 2008.
D. Hong and Cheng, K. - T. Tim, Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links, in VLSI Test Symposium, 2008. VTS 2008. 26th IEEE, 2008.
C. - K. Ong, Hong, D., Cheng, K. - T. Tim, and Wang, L. - C., A clock-less jitter spectral analysis technique, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 55, pp. 2263–2272, 2008.
S. Shamshiri, Lisherness, P., Pan, S. - J., and Cheng, K. - T. Tim, A cost analysis framework for multi-core systems with spares, in Test Conference, 2008. ITC 2008. IEEE International, 2008.
H. - M. Sherman Chang, Lin, M. - S., and Cheng, K. - T. Tim, Digitally-assisted analog/RF testing for mixed-signal SoCs, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.
T. - C. Jim Huang, Cheng, K. - T. Tim, Tseng, H. - Y., and Kung, C. - P., Reliability analysis for flexible electronics: Case study of integrated a-Si: H TFT scan driver, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 4, no. 3, 2008.
S. Mirzaeian, Zheng, F., and Cheng, K. - T. Tim, RTL error diagnosis using a word-level SAT-solver, in Test Conference, 2008. ITC 2008. IEEE International, 2008.
M. Gao, Chang, H. - M. Sherman, Lisherness, P., and Cheng, K. - T. Tim, Time-Multiplexed Online Checking: A Feasibility Study, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.

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