Biblio

Export 152 results:
Author [ Year(Asc)]
2009
K. - T. Tim Cheng and Chang, H. - M. Sherman, Test strategies for adaptive equalizers, in Custom Integrated Circuits Conference, 2009. CICC'09. IEEE, 2009.
S. Shamshiri and Cheng, K. - T. Tim, Yield and cost analysis of a reliable NoC, in VLSI Test Symposium, 2009. VTS'09. 27th IEEE, 2009.
2008
D. Hong and Cheng, K. - T. Tim, Accurate Bit-Error-Rate estimation for efficient high speed I/O testing, in Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on, 2008.
D. Hong and Cheng, K. - T. Tim, Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links, in VLSI Test Symposium, 2008. VTS 2008. 26th IEEE, 2008.
C. - K. Ong, Hong, D., Cheng, K. - T. Tim, and Wang, L. - C., A clock-less jitter spectral analysis technique, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 55, pp. 2263–2272, 2008.
S. Shamshiri, Lisherness, P., Pan, S. - J., and Cheng, K. - T. Tim, A cost analysis framework for multi-core systems with spares, in Test Conference, 2008. ITC 2008. IEEE International, 2008.
H. - M. Sherman Chang, Lin, M. - S., and Cheng, K. - T. Tim, Digitally-assisted analog/RF testing for mixed-signal SoCs, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.
T. - C. Huang, Cheng, K. - T. Tim, Tseng, H. - Y., and Kung, C. - P., Reliability analysis for flexible electronics: Case study of integrated a-Si: H TFT scan driver, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 4, no. 3, 2008.
S. Mirzaeian, Zheng, F., and Cheng, K. - T. Tim, RTL error diagnosis using a word-level SAT-solver, in Test Conference, 2008. ITC 2008. IEEE International, 2008.
M. Gao, Chang, H. - M. Sherman, Lisherness, P., and Cheng, K. - T. Tim, Time-Multiplexed Online Checking: A Feasibility Study, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.
2007
D. Hong and Cheng, K. - T. Tim, An accurate jitter estimation technique for efficient high speed I/O testing, in Asian Test Symposium, 2007. ATS'07. 16th, 2007.
T. - C. Huang and Cheng, K. - T. Tim, Design for Printability for Flexible Electronics: Self-Tunable Cell-Library Design, in International Symposium for Flexible Electronics and Displays (ISFED), Hsinchu, Taiwan, 2007.
F. Zheng, Cheng, K. - T. Tim, Yan, X., Moondanos, J., and Hanna, Z., An efficient diagnostic test pattern generation framework using boolean satisfiability, in Asian Test Symposium, 2007. ATS'07. 16th, 2007.
S. - J. Pan and Cheng, K. - T. Tim, A framework for system reliability analysis considering both system error tolerance and component test quality, in Proceedings of the conference on Design, automation and test in Europe, 2007.
M. C. - T. Chao, Cheng, K. - T. Tim, Wang, S., Chakradhar, S. T., and Wei, W. - L., A hybrid scheme for compacting test responses with unknown values, in Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007.
Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Multiple-fault diagnosis based on adaptive diagnostic test pattern generation, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 932–942, 2007.
K. Yang and Cheng, K. - T. Tim, Silicon Debug for Timing Errors, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 2084–2088, 2007.
M. Lin and Cheng, K. - T. Tim, Testable design for advanced serial-link transceivers, in Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE'07, 2007.
2006
K. - T. Tim Cheng, Automatic Test Pattern Generation, in EDA for IC System Design, Verification, and Testing, CRC Press, 2006.
D. Hong and Cheng, K. - T. Tim, Bit error rate estimation for improving jitter testing of high-speed serial links, in Test Conference, 2006. ITC'06. IEEE International, 2006.
D. Hong, Ong, C. - K., and Cheng, K. - T. Tim, Bit-error-rate estimation for high-speed serial links, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 53, pp. 2616–2627, 2006.
M. C. - T. Chao, Wang, S., Chakradhar, S. T., Wei, W., and Cheng, K. - T. Tim, Coverage loss by using space compactors in presence of unknown values, in Proceedings of the conference on Design, automation and test in Europe: Proceedings, 2006, pp. 1053–1054.
K. Yang and Cheng, K. - T. Tim, Efficient identification of multi-cycle false path, in Proceedings of the 2006 Asia and South Pacific Design Automation Conference, 2006, pp. 360–365.
S. - J. Pan, Cheng, K. - T. Tim, Moondanos, J., and Hanna, Z., Generation of shorter sequences for high resolution error diagnosis using sequential sat, in Proceedings of the 2006 Asia and South Pacific Design Automation Conference, 2006, pp. 25–29.
F. Lu and Cheng, K. - T. Tim, IChecker: An efficient checker for inductive invariants, in High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International, 2006.

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