Biblio

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L
P. Lisherness and Cheng, K. - T. Tim, Improving validation coverage metrics to account for limited observability, in Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 2012.
P. Lisherness and Cheng, K. - T. Tim, An instrumented observability coverage method for system validation, in High Level Design Validation and Test Workshop, 2009. HLDVT 2009. IEEE International, 2009.
P. Lisherness, Lesperance, N., and Cheng, K. - T. Tim, Mutation analysis with coverage discounting, in Design, Automation Test in Europe Conference (DATE), 2013.PDF icon DATE13.pdf (167.64 KB)
P. Lisherness and Cheng, K. - T. Tim, SCEMIT: A SystemC error and mutation injection tool, in Design Automation Conference (DAC), 2010 47th ACM/IEEE, 2010.
P. Lisherness and Cheng, K. - T. Tim, Coverage discounting: A generalized approach for testbench qualification, in High Level Design Validation and Test Workshop (HLDVT), 2011 IEEE International, 2011.
C. - M. Lo, Huang, T. - C. Jim, Chiang, C. - Y., Hou, J., and Cheng, K. - T. Tim, A Portable Multi-pitch e-Drum Based on Printed Flexible Pressure Sensors, in Proceedings of the Conference on Design, Automation and Test in Europe, 3001 Leuven, Belgium, Belgium, 2010.
F. Lu and Cheng, K. - T. Tim, SEChecker: A Sequential Equivalence Checking Framework Based on th Invariants, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 17, pp. 733–746, 2009.
F. Lu and Cheng, K. - T. Tim, Sequential equivalence checking based on K-th invariants and circuit SAT solving, in High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International, 2005, pp. 45–51.
F. Lu and Cheng, K. - T. Tim, IChecker: An efficient checker for inductive invariants, in High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International, 2006.
F. Lu, Iyer, M. K., Parthasarathy, G., Wang, L. - C., Cheng, K. - T. Tim, and Chen, K. - C., An efficient sequential SAT solver with improved search strategies, in Proceedings of the conference on Design, Automation and Test in Europe-Volume 2, 2005, pp. 1102–1107.
M
S. Mirzaeian, Zheng, F., and Cheng, K. - T. Tim, RTL error diagnosis using a word-level SAT-solver, in Test Conference, 2008. ITC 2008. IEEE International, 2008.
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C. - K. Ong, Hong, D., Cheng, K. - T. Tim, and Wang, L. - C., A clock-less jitter spectral analysis technique, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 55, pp. 2263–2272, 2008.

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