Biblio

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H
T. - C. Jim Huang, Fukuda, K., Lo, C. - M., Yeh, Y. - H., Sekitani, T., Someya, T., and Cheng, K. - T. Tim, Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics, Electron Devices, IEEE Transactions on, vol. 58, pp. 141-150, 2011.
T. - C. Jim Huang, Lei, T., Shao, L., Sivapurapu, S., Swaminathan, M., Li, S., Bao, Z., Cheng, K. - T. Tim, and Beausoleil, R. G., Process Design Kit and Design Automation for Flexible Hybrid Electronics, in SID International Symposium, 2019. (invited paper), 2019.PDF icon FHEPDK_Jim_Huang_SID19_for_review_v1.pdf (665.97 KB)
T. - C. Jim Huang and Cheng, K. - T. Tim, Design for low power and reliable flexible electronics: Self-tunable cell-library design, Display Technology, Journal of, vol. 5, pp. 206–215, 2009.
T. - C. Jim Huang, Huang, J. - L., and Cheng, K. - T. Tim, Robust circuit design for flexible electronics, IEEE Design and Test of Computers, vol. 28, pp. 8–15, 2011.
C. - K. Hsu, Lin, F., Cheng, K. - T. Tim, Zhang, W., Li, X., Carulli, J. M., and Butler, K. M., Test data analytics - Exploring spatial and test-item correlations in production test data, in Test Conference (ITC), 2013 IEEE International, 2013.
C. - K. Hsu, Sarson, P., Leisenberger, F., Schatzberger, G., Carulli, J., Siddhartha, S., and Cheng, K. - T. Tim, Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages, in IEEE International Test Conference (ITC), 2016.PDF icon itc16.pdf (407.86 KB)
D. Hong and Cheng, K. - T. Tim, Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links, in VLSI Test Symposium, 2008. VTS 2008. 26th IEEE, 2008.
D. Hong and Cheng, K. - T. Tim, Accurate Bit-Error-Rate estimation for efficient high speed I/O testing, in Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on, 2008.
D. Hong and Cheng, K. - T. Tim, Efficient test methodologies for high-speed serial links, vol. 51. Springer Science & Business Media, 2009.
D. Hong and Cheng, K. - T. Tim, Bit error rate estimation for improving jitter testing of high-speed serial links, in Test Conference, 2006. ITC'06. IEEE International, 2006.
D. Hong, Ong, C. - K., and Cheng, K. - T. Tim, Bit-error-rate estimation for high-speed serial links, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 53, pp. 2616–2627, 2006.
D. Hong and Cheng, K. - T. Tim, A two-tone test method for continuous-time adaptive equalizers, in Efficient Test Methodologies for High-Speed Serial Links, Springer, 2010, pp. 75–87.
D. Hong and Cheng, K. - T. Tim, An accurate jitter estimation technique for efficient high speed I/O testing, in Asian Test Symposium, 2007. ATS'07. 16th, 2007.
G
A. Ghofrani, Parikh, R., Shamshiri, S., DeOrio, A., Cheng, K. - T. Tim, and Bertacco, V., Comprehensive online defect diagnosis in on-chip networks., in VLSI Test Symposium (VTS), 2012.PDF icon VTS12_cr.pdf (710.92 KB)
A. Ghofrani, Lastras-Montano, M. Angel, and Cheng, K. - T. Tim, Towards data reliable crossbar-based memristive memories, in Test Conference (ITC), 2013 IEEE International, 2013.PDF icon ITC'13_CR.pdf (2.68 MB)
A. Ghofrani, Lastras-Montano, M. Angel, Gaba, S., Payand, M., Lu, W., Theogarajan, L., and Cheng, K. - T. Tim, A low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 12, no. 1, 2015.PDF icon JETC15.pdf (3.27 MB)
A. Ghofrani, Lastras-Montano, M. Angel, and Cheng, K. - T. Tim, Toward Large-Scale Access-Transistor-Free Memristive Crossbars, in Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific, 2015.PDF icon ASPDAC_invited.pdf (3.38 MB)
A. Ghofrani, Rahimi, A., Lastras-Montano, M. Angel, Benini, L., Gupta, R. K., and Cheng, K. - T. Tim, Associative Memristive Memory for Approximate Computing in GPUs, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. PP, no. 99, 2016.PDF icon JETCAS_16.pdf (6.36 MB)
A. Ghofrani, Lastras-Montano, M. Angel, Wang, Y., and Cheng, K. - T. Tim, In-place Repair for Resistive Memories Utilizing Complementary Resistive Switches, International Symposium on Low Power Electronics and Design (ISLPED). ACM, San Diego, CA, USA, 2016.PDF icon ISLPED_16.pdf (4.14 MB)
M. Gao, Chang, H. - M. Sherman, Lisherness, P., and Cheng, K. - T. Tim, Time-Multiplexed Online Checking: A Feasibility Study, in Asian Test Symposium, 2008. ATS'08. 17th, 2008.
M. Gao, Lisherness, P., and Cheng, K. - T. Tim, Adaptive test selection for post-silicon timing validation: A data mining approach, in Test Conference (ITC), 2012 IEEE International, 2012.
M. Gao and Cheng, K. - T. Tim, Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder, in Asian Test Symposium, 2009. ATS '09., 2009.
L. Gao, Merrikh-Bayat, F., Alibart, F., Guo, X., Hoskins, B. D., Cheng, K. - T. Tim, and Strukov, D. B., Digital-to-analog and analog-to-digital conversion with metal oxide memristors for ultra-low power computing, in Nanoscale Architectures (NANOARCH), 2013 IEEE/ACM International Symposium on, 2013.
M. Gao and Cheng, K. - T. Tim, A case study of Time-Multiplexed Assertion Checking for post-silicon debugging, in High Level Design Validation and Test Workshop (HLDVT), 2010 IEEE International, 2010.
M. Gao, Lisherness, P., and Cheng, K. - T. Tim, Post-silicon Bug Detection for Variation Induced Electrical Bugs, in Proceedings of the 16th Asia and South Pacific Design Automation Conference, Piscataway, NJ, USA, 2011.

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