Biblio

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2011
K. Fukuda, Sekitani, T., Yokota, T., Kuribara, K., Huang, T. - C. Jim, Sakurai, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., “Organic pseudo-CMOS circuits for low-voltage large-gain high-speed operation”, Electron Device Letters, IEEE, vol. 32, pp. 1448–1450, 2011.
K. Fukuda, Huang, T. - C. Jim, Kuribara, K., Yokota, T., Sekitani, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., “Organic Pseudo-CMOS for 2V Operational High-Speed Circuits”. 2011.
M. Gao, Lisherness, P., and Cheng, K. - T. Tim, “Post-silicon Bug Detection for Variation Induced Electrical Bugs”, in Proceedings of the 16th Asia and South Pacific Design Automation Conference, Piscataway, NJ, USA, 2011.
T. - C. Jim Huang, Fukuda, K., Lo, C. - M., Yeh, Y. - H., Sekitani, T., Someya, T., and Cheng, K. - T. Tim, “Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics”, Electron Devices, IEEE Transactions on, vol. 58, pp. 141-150, 2011.
T. - C. Jim Huang, Huang, J. - L., and Cheng, K. - T. Tim, “Robust circuit design for flexible electronics”, IEEE Design and Test of Computers, vol. 28, pp. 8–15, 2011.
H. - M. Sherman Chang, Cheng, K. - T. Tim, Zhang, W., Li, X., and Butler, K. M., “Test cost reduction through performance prediction using virtual probe”, in Test Conference (ITC), 2011 IEEE International, 2011.
H. - M. Sherman Chang, Cheng, K. - T. Tim, Zhang, W., Li, X., and Butler, K. M., “Test cost reduction through performance prediction using virtual probe”, in Test Conference (ITC), 2011 IEEE International, 2011.
M. Gao, Chang, H. - M. Sherman, Lisherness, P., and Cheng, K. - T. Tim, “Time-multiplexed online checking”, Computers, IEEE Transactions on, vol. 60, pp. 1300–1312, 2011.
M. Gao, Chang, H. - M. Sherman, Lisherness, P., and Cheng, K. - T. Tim, “Time-multiplexed online checking”, Computers, IEEE Transactions on, vol. 60, pp. 1300–1312, 2011.
2010
M. Abbas, Cheng, K. - T. Tim, Furukawa, Y., Komatsu, S., and Asada, K., “An Automatic Test Generation Framework for Digitally-assisted Adaptive Equalizers in High-speed Serial Links”, in Proceedings of the Conference on Design, Automation and Test in Europe, 3001 Leuven, Belgium, Belgium, 2010.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, “Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study”, Journal of Electronic Testing, vol. 26, pp. 59-71, 2010.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, “Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study”, Journal of Electronic Testing, vol. 26, pp. 59-71, 2010.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, “Calibration-assisted production testing for digitally-calibrated ADCs”, in VLSI Test Symposium (VTS), 2010 28th, 2010.
H. - M. Sherman Chang, Lin, K. - Y., and Cheng, K. - T. Tim, “Calibration-assisted production testing for digitally-calibrated ADCs”, in VLSI Test Symposium (VTS), 2010 28th, 2010.
M. Gao and Cheng, K. - T. Tim, “A case study of Time-Multiplexed Assertion Checking for post-silicon debugging”, in High Level Design Validation and Test Workshop (HLDVT), 2010 IEEE International, 2010.
K. - T. Tim Cheng and Huang, T. - C. Jim, “Design, analysis, and test of low-power and reliable flexible electronics”, in VLSI Test Symposium (VTS), 2010 28th, 2010.
H. - M. Sherman Chang, Huang, J. - L., Kwai, D. - M., Cheng, K. - T. Tim, and Wu, C. - W., “An Error Tolerance Scheme for 3D CMOS Imagers”, in Proceedings of the 47th Design Automation Conference, New York, NY, USA, 2010.
H. - M. Sherman Chang, Huang, J. - L., Kwai, D. - M., Cheng, K. - T. Tim, and Wu, C. - W., “An Error Tolerance Scheme for 3D CMOS Imagers”, in Proceedings of the 47th Design Automation Conference, New York, NY, USA, 2010.
S. Shamshiri and Cheng, K. - T. Tim, “Error-locality-aware linear coding to correct multi-bit upsets in SRAMs”, in Test Conference (ITC), 2010 IEEE International, 2010.
H. - M. Sherman Chang and Cheng, K. - T. Tim, “Low-cost quality assurance techniques for high-performance mixed-signal/RF circuits and systems”, in Test Conference (ITC), 2010 IEEE International, 2010.
H. - M. Sherman Chang and Cheng, K. - T. Tim, “Low-cost quality assurance techniques for high-performance mixed-signal/RF circuits and systems”, in Test Conference (ITC), 2010 IEEE International, 2010.
S. Shamshiri and Cheng, K. - T. Tim, “Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy”, in VLSI Test Symposium (VTS), 2010 28th, 2010.
H. Li, Xu, D., Han, Y., Cheng, K. - T. Tim, and Li, X., “nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications”, in Test Conference (ITC), 2010 IEEE International, 2010.
C. - M. Lo, Huang, T. - C. Jim, Chiang, C. - Y., Hou, J., and Cheng, K. - T. Tim, “A Portable Multi-pitch e-Drum Based on Printed Flexible Pressure Sensors”, in Proceedings of the Conference on Design, Automation and Test in Europe, 3001 Leuven, Belgium, Belgium, 2010.
C. - M. Lo, Huang, T. - C. Jim, Chiang, C. - Y., Hou, J., and Cheng, K. - T. Tim, “A Portable Multi-pitch e-Drum Based on Printed Flexible Pressure Sensors”, in Proceedings of the Conference on Design, Automation and Test in Europe, 3001 Leuven, Belgium, Belgium, 2010.

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