Biblio

Export 151 results:
Author [ Year(Asc)]
2006
Y. - C. Lin and Cheng, K. - T. Tim, Multiple-fault diagnosis based on single-fault activation and single-output observation, in Design, Automation and Test in Europe, 2006. DATE'06. Proceedings, 2006, vol. 1, pp. 1–6.
Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Pseudofunctional testing, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 1535–1546, 2006.
C. H. - P. Wen, Wang, L. C., and Cheng, K. - T. Tim, Simulation-based functional test generation for embedded processors, Computers, IEEE Transactions on, vol. 55, pp. 1335–1343, 2006.
K. Roy, Mak, T. M., and Cheng, K. - T. Tim, Test consideration for nanometer-scale CMOS circuits, Design & Test of Computers, IEEE, vol. 23, pp. 128–136, 2006.
M. Lin and Cheng, K. - T. Tim, Testable design for adaptive linear equalizer in high-speed serial links, in Test Conference, 2006. ITC'06. IEEE International, 2006.
K. Yang and Cheng, K. - T. Tim, Timing-reasoning-based delay fault diagnosis, in Proceedings of the conference on Design, automation and test in Europe: Proceedings, 2006, pp. 418–423.
Y. - C. Lin and Cheng, K. - T. Tim, A unified approach to test generation and test data volume reduction, in Test Conference, 2006. ITC'06. IEEE International, 2006.
M. C. - T. Chao, Cheng, K. - T. Tim, Wang, S., Chakradhar, S., and Wei, W. - L., Unknown-tolerance analysis and test-quality control for test response compaction using space compactors, in Proceedings of the 43rd annual Design Automation Conference, 2006.
2005
Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Accurate diagnosis of multiple faults, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 153–156.
M. C. - T. Chao, Wang, S., Chakradhar, S. T., and Cheng, K. - T. Tim, ChiYun compact: a novel test compaction technique for responses with unknown values, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 147–152.
Y. - C. Lin, Lu, F., Yang, K., and Cheng, K. - T. Tim, Constraint extraction for pseudo-functional scan-based delay testing, in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, 2005, pp. 166–171.
M. K. Iyer, Parthasarathy, G., and Cheng, K. - T. Tim, Efficient conflict-based learning in an RTL circuit constraint solver, in Design, Automation and Test in Europe, 2005. Proceedings, 2005, pp. 666–671.
F. Lu, Iyer, M. K., Parthasarathy, G., Wang, L. - C., Cheng, K. - T. Tim, and Chen, K. - C., An efficient sequential SAT solver with improved search strategies, in Proceedings of the conference on Design, Automation and Test in Europe-Volume 2, 2005, pp. 1102–1107.
K. - T. Tim Cheng, Embedded Software-Based Self-Testing for SoC Design, in Embedded Systems Handbook, CRC Press, 2005, pp. 28-1-28-19.
Q. Zhu, Avidan, S., and Cheng, K. - T. Tim, Learning a sparse, corner-based representation for time-varying background modelling, in Computer Vision, 2005. ICCV 2005. Tenth IEEE International Conference on, 2005.
M. Lin, Cheng, K. - T. Tim, Hsu, J., Sun, M. C., Chen, J., and Lu, S., Production-oriented interface testing for PCI-Express by enhanced loop-back technique, in Test Conference, 2005. Proceedings. ITC 2005. IEEE International, 2005, p. 10–pp.
Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Pseudo-functional scan-based bist for delay fault, in VLSI Test Symposium, 2005. Proceedings. 23rd IEEE, 2005, pp. 229–234.
M. C. - T. Chao, Wang, S., Chakradhar, S. T., and Cheng, K. - T. Tim, Response shaper: a novel technique to enhance unknown tolerance for output response compaction, in Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on, 2005, pp. 80–87.
G. Parthasarathy, Iyer, M. K., Cheng, K. - T. Tim, and Brewer, F., RTL SAT simplification by boolean and interval arithmetic reasoning, in Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, 2005, pp. 297–302.
F. Lu and Cheng, K. - T. Tim, Sequential equivalence checking based on K-th invariants and circuit SAT solving, in High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International, 2005, pp. 45–51.
C. H. - P. Wen, Wang, L. - C., Cheng, K. - T. Tim, Yang, K., Liu, W. - T., Chen, J. - J., and , On a software-based self-test methodology and its application, in VLSI Test Symposium, 2005. Proceedings. 23rd IEEE, 2005, pp. 107–113.
K. Yang, Wang, L. - C., Cheng, K. - T. Tim, and Kundu, S., On statistical correlation based path selection for timing validation, in VLSI Design, Automation and Test, 2005.(VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on, 2005, pp. 8–11.
G. Parthasarathy, Iyer, M. K., Cheng, K. - T. Tim, and Brewer, F., Structural search for RTL with predicate learning, in Proceedings of the 42nd annual Design Automation Conference, 2005, pp. 451–456.
T. Feng, Wang, L. - C., Cheng, K. - T. Tim, and Lin, C. - C. Andy, Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 10, pp. 627–650, 2005.
C. - T. Wu, Cheng, K. - T. Tim, Zhu, Q., and Wu, Y. - L., Using visual features for anti-spam filtering, in Image Processing, 2005. ICIP 2005. IEEE International Conference on, 2005, vol. 3, p. III–509.

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