Biblio
] , Efficient test methodologies for high-speed serial links, vol. 51. Springer Science & Business Media, 2009.
, “Bit error rate estimation for improving jitter testing of high-speed serial links”, in Test Conference, 2006. ITC'06. IEEE International, 2006.
, “Bit-error-rate estimation for high-speed serial links”, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 53, pp. 2616–2627, 2006.
, “A two-tone test method for continuous-time adaptive equalizers”, in Efficient Test Methodologies for High-Speed Serial Links, Springer, 2010, pp. 75–87.
, “An accurate jitter estimation technique for efficient high speed I/O testing”, in Asian Test Symposium, 2007. ATS'07. 16th, 2007.
, “Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links”, in VLSI Test Symposium, 2008. VTS 2008. 26th IEEE, 2008.
, “Accurate Bit-Error-Rate estimation for efficient high speed I/O testing”, in Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on, 2008.