Biblio

Export 4 results:
Author [ Year(Desc)]
Filters: Author is Parthasarathy, Ganapathy  [Clear All Filters]
2005
M. K. Iyer, Parthasarathy, G., and Cheng, K. - T. Tim, Efficient conflict-based learning in an RTL circuit constraint solver, in Design, Automation and Test in Europe, 2005. Proceedings, 2005, pp. 666–671.
F. Lu, Iyer, M. K., Parthasarathy, G., Wang, L. - C., Cheng, K. - T. Tim, and Chen, K. - C., An efficient sequential SAT solver with improved search strategies, in Proceedings of the conference on Design, Automation and Test in Europe-Volume 2, 2005, pp. 1102–1107.
G. Parthasarathy, Iyer, M. K., Cheng, K. - T. Tim, and Brewer, F., RTL SAT simplification by boolean and interval arithmetic reasoning, in Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, 2005, pp. 297–302.
G. Parthasarathy, Iyer, M. K., Cheng, K. - T. Tim, and Brewer, F., Structural search for RTL with predicate learning, in Proceedings of the 42nd annual Design Automation Conference, 2005, pp. 451–456.