Biblio

Export 20 results:
[ Author(Asc)] Year
Filters: First Letter Of Last Name is H  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
H
T. - C. Jim Huang, Fukuda, K., Lo, C. - M., Yeh, Y. - H., Sekitani, T., Someya, T., and Cheng, K. - T. Tim, “Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics”, Electron Devices, IEEE Transactions on, vol. 58, pp. 141-150, 2011.
T. - C. Jim Huang and Cheng, K. - T. Tim, “Design for Printability for Flexible Electronics: Self-Tunable Cell-Library Design”, in International Symposium for Flexible Electronics and Displays (ISFED), Hsinchu, Taiwan, 2007.
T. - C. Jim Huang, Cheng, K. - T. Tim, Tseng, H. - Y., and Kung, C. - P., “Reliability analysis for flexible electronics: Case study of integrated a-Si: H TFT scan driver”, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 4, no. 3, 2008.
T. - C. Jim Huang, Huang, J. - L., and Cheng, K. - T. Tim, “Design, Automation, and Test for Low-Power and Reliable Flexible Electronics”, Foundations and Trends in Electronic Design Automation, vol. 9, pp. 99-210, 2015.
T. - C. Jim Huang and Cheng, K. - T. Tim, “Design for low power and reliable flexible electronics: Self-tunable cell-library design”, Display Technology, Journal of, vol. 5, pp. 206–215, 2009.
T. - C. Jim Huang, Li, C., Wu, R., Chen, C. - H., Fiorentino, M., Cheng, K. - T. Tim, Palermo, S., and Beausoleil, R. G., “DWDM Nanophotonic Interconnects: Toward Terabit/s Chip-Scale Serial Link”, in International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, Colorado, 2015.PDF icon DWDM_nanophotnic link_JimHuang_camera_ready.pdf (1.23 MB)
T. - C. Jim Huang, Shao, L., Lei, T., Beausoleil, R. G., Bao, Z., and Cheng, K. - T. Tim, “Robust Design and Design Automation for Flexible Hybrid Electronics”, in International Symposium on Circuits and Systems (ISCAS), 2017.
T. - C. Jim Huang, Lei, T., Shao, L., Sivapurapu, S., Swaminathan, M., Li, S., Bao, Z., Cheng, K. - T. Tim, and Beausoleil, R. G., “Process Design Kit and Design Automation for Flexible Hybrid Electronics”, in Design Automation And Test in Europe (Invited Paper), Florence, Italy, 2019.PDF icon DATE19_Jim_submission.pdf (2.4 MB)
T. - C. Jim Huang, Lei, T., Shao, L., Sivapurapu, S., Swaminathan, M., Li, S., Bao, Z., Cheng, K. - T. Tim, and Beausoleil, R. G., “Process Design Kit and Design Automation for Flexible Hybrid Electronics”, in SID International Symposium, 2019. (invited paper), 2019.PDF icon FHEPDK_Jim_Huang_SID19_for_review_v1.pdf (665.97 KB)
T. - C. Jim Huang, Huang, J. - L., and Cheng, K. - T. Tim, “Robust circuit design for flexible electronics”, IEEE Design and Test of Computers, vol. 28, pp. 8–15, 2011.
T. - C. Jim Huang, Fukuda, K., Lo, C. - M., Yeh, Y. - H., Sekitani, T., Someya, T., and Cheng, K. - T. Tim, “Pseudo-CMOS: A novel design style for flexible electronics”, in Design, Automation Test in Europe Conference Exhibition (DATE), 2010, 2010.
C. - K. Hsu, Lin, F., Cheng, K. - T. Tim, Zhang, W., Li, X., Carulli, J. M., and Butler, K. M., “Test data analytics - Exploring spatial and test-item correlations in production test data”, in Test Conference (ITC), 2013 IEEE International, 2013.
C. - K. Hsu, Sarson, P., Leisenberger, F., Schatzberger, G., Carulli, J., Siddhartha, S., and Cheng, K. - T. Tim, “Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages”, in IEEE International Test Conference (ITC), 2016.PDF icon itc16.pdf (407.86 KB)
D. Hong and Cheng, K. - T. Tim, Efficient test methodologies for high-speed serial links, vol. 51. Springer Science & Business Media, 2009.
D. Hong and Cheng, K. - T. Tim, “Bit error rate estimation for improving jitter testing of high-speed serial links”, in Test Conference, 2006. ITC'06. IEEE International, 2006.
D. Hong, Ong, C. - K., and Cheng, K. - T. Tim, “Bit-error-rate estimation for high-speed serial links”, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 53, pp. 2616–2627, 2006.
D. Hong and Cheng, K. - T. Tim, “A two-tone test method for continuous-time adaptive equalizers”, in Efficient Test Methodologies for High-Speed Serial Links, Springer, 2010, pp. 75–87.
D. Hong and Cheng, K. - T. Tim, “An accurate jitter estimation technique for efficient high speed I/O testing”, in Asian Test Symposium, 2007. ATS'07. 16th, 2007.
D. Hong and Cheng, K. - T. Tim, “Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links”, in VLSI Test Symposium, 2008. VTS 2008. 26th IEEE, 2008.
D. Hong and Cheng, K. - T. Tim, “Accurate Bit-Error-Rate estimation for efficient high speed I/O testing”, in Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on, 2008.