Biblio

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F. Lan, Wu, R., Zhang, C., Pan, Y., and Cheng, K. - T. Tim, DLPS: Dynamic Laser Power Scaling for Optical Network-on-Chip, in Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba/Tokyo, Japan, 2017.PDF icon laser_final.pdf (2.21 MB)
M. Angel Lastras-Montano, Ghofrani, A., and Cheng, K. - T. Tim, HReRAM: A Hybrid Reconfigurable Resistive Random-Access Memory, Proceedings Design, Automation, and Test in Europe (DATE), IEEE, 2015.PDF icon DATE15_1.pdf (5.59 MB)
M. Angel Lastras-Montano, Ghofrani, A., and Cheng, K. - T. Tim, Architecting Energy Efficient Crossbar-based Memristive Random Access Memories, in ACM/IEEE Internation Symposium on Nano-scale Architectures (NANOARCH'15), 2015.PDF icon NANOARCH15.pdf (3.42 MB)
M. Angel Lastras-Montano, Ghofrani, A., and Cheng, K. - T. Tim, Architecting Low Power Crossbar-Based Memristive RAM, in Non-Volatile Memory Workshop, San Diego, USA, 2013.PDF icon NVMW13.pdf (721.83 KB)
M. Angel Lastras-Montano, Ghofrani, A., and Cheng, K. - T. Tim, A Low-Power Hybrid Reconfigurable Architecture For Resistive Random-Access Memories, in International Symposium on High-Performance Computer Architecture (HPCA), Barcelona, Spain, 2016.PDF icon HPCA16_1.pdf (6.47 MB)
M. Angel Lastras-Montano, Chakrabarti, B., Strukov, D. B., and Cheng, K. - T. Tim, 3D-DPE: A 3D High-Bandwidth Dot-Product Engine for High-Performance Neuromorphic Computing, Design, Automation and Test in Europe (DATE). Lausanne, Switzerland, 2017.
T. Lei, Shao, L., Zheng, Y., Pitner, G., Fang, G., Zhu, C., Li, S., Beausoleil, R. G., Wong, H. - S. Philip, Huang, T. - C. Jim, Cheng, K. - T. Tim, and Bao, Z., Low-voltage High-performance Flexible Digital and Analog Circuits based on Ultrahigh-purity Semiconducting Carbon Nanotubes, Nature Communication, 2019.PDF icon s41467-019-10145-9.pdf (3.65 MB)
N. Lesperance, Kulkarni, S., and Cheng, K. - T. Tim, Hardware Trojan Detection Using Exhaustive Testing of k-bit Subspaces, in Asia and South Pacific Design Automation Conference (ASP-DAC), 2015.PDF icon ASPDAC2015.pdf (508.45 KB)
H. Li, Xu, D., Han, Y., Cheng, K. - T. Tim, and Li, X., nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications, in Test Conference (ITC), 2010 IEEE International, 2010.
F. Lin, Hsu, C. - K., and Cheng, K. - T. Tim, AdaTest: An Efficient Statistical Test Framework for Test Escape Screening, in International Test Conference (ITC), Anaheim, CA, 2015.PDF icon itc15.pdf (273 KB)
F. Lin, Hsu, C. - K., Busetto, A. Giovanni, and Cheng, K. - T. Tim, Pairwise Proximity-Based Features for Test Escape Screening, in International Conference on Computer-Aided Design (ICCAD), Austin, TX, 2015.PDF icon iccad15.pdf (792.61 KB)
F. Lin and Cheng, K. - T. Tim, An Artificial Neural Network Approach for Screening Test Escapes, Asia and South Pacific Design Automation Conference (ASP-DAC). Chiba/Tokyo, Japan, 2017.PDF icon aspdac17.pdf (810.67 KB)
Y. - C. Lin, Lu, F., Yang, K., and Cheng, K. - T. Tim, Constraint extraction for pseudo-functional scan-based delay testing, in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, 2005, pp. 166–171.
Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Pseudo-functional scan-based bist for delay fault, in VLSI Test Symposium, 2005. Proceedings. 23rd IEEE, 2005, pp. 229–234.
Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Accurate diagnosis of multiple faults, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 153–156.
M. Lin, Cheng, K. - T. Tim, Hsu, J., Sun, M. C., Chen, J., and Lu, S., Production-oriented interface testing for PCI-Express by enhanced loop-back technique, in Test Conference, 2005. Proceedings. ITC 2005. IEEE International, 2005, p. 10–pp.
Y. - C. Lin and Cheng, K. - T. Tim, Multiple-fault diagnosis based on single-fault activation and single-output observation, in Design, Automation and Test in Europe, 2006. DATE'06. Proceedings, 2006, vol. 1, pp. 1–6.
Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Pseudofunctional testing, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 1535–1546, 2006.
Y. - C. Lin and Cheng, K. - T. Tim, A unified approach to test generation and test data volume reduction, in Test Conference, 2006. ITC'06. IEEE International, 2006.
M. Lin and Cheng, K. - T. Tim, Testable design for adaptive linear equalizer in high-speed serial links, in Test Conference, 2006. ITC'06. IEEE International, 2006.
M. Lin and Cheng, K. - T. Tim, Testable design for advanced serial-link transceivers, in Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE'07, 2007.
Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Multiple-fault diagnosis based on adaptive diagnostic test pattern generation, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 932–942, 2007.
F. Lin, Hsu, C. - K., and Cheng, K. - T. Tim, Feature engineering with canonical analysis for effective statistical tests screening test escapes, in Test Conference (ITC), 2014 IEEE International, 2014.PDF icon itc14.pdf (4.28 MB)
F. Lin, Hsu, C. - K., and Cheng, K. - T. Tim, Learning from Production Test Data: Correlation Exploration and Feature Engineering, in Test Symposium (ATS), 2014 IEEE 23rd Asian, 2014.PDF icon ats14.pdf (2.45 MB)
P. Lisherness and Cheng, K. - T. Tim, An instrumented observability coverage method for system validation, in High Level Design Validation and Test Workshop, 2009. HLDVT 2009. IEEE International, 2009.

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