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K. Yang, Wang, L. - C., Cheng, K. - T. Tim, and Kundu, S., On statistical correlation based path selection for timing validation, in VLSI Design, Automation and Test, 2005.(VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on, 2005, pp. 8–11.
K. Yang and Cheng, K. - T. Tim, Efficient identification of multi-cycle false path, in Proceedings of the 2006 Asia and South Pacific Design Automation Conference, 2006, pp. 360–365.
K. Yang and Cheng, K. - T. Tim, Timing-reasoning-based delay fault diagnosis, in Proceedings of the conference on Design, automation and test in Europe: Proceedings, 2006, pp. 418–423.
K. Yang and Cheng, K. - T. Tim, Silicon Debug for Timing Errors, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 2084–2088, 2007.