Biblio

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2016
N. Fern, San, I., Koc, C. Kaya, and Cheng, K. - T. Tim, Hardware Trojans in Incompletely Specified On-chip Bus Systems, in Design, Automation, Test in Europe (DATE), 2016.PDF icon DATE16_4page_aff.pdf (315.73 KB)
N. Fern, San, I., Koc, C. Kaya, and Cheng, K. - T. Tim, Hiding Hardware Trojan Communication Channels in Partially Specified SoC Bus Functionality, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. PP, 2016.PDF icon TCAD.pdf (2.23 MB)
I. San, Fern, N., Koc, C. Kaya, and Cheng, K. - T. Tim, Trojans Modifying Soft-Processor Instruction Sequences Embedded in FPGA Bitstreams, in Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL), 2016.PDF icon FPL16.pdf (170.74 KB)
2013
H. - M. Chang Chang, Huang, J. - L., Kwai, D. - M., Cheng, K. - T. Tim, and Wu, C. - W., Low-cost error tolerance scheme for 3-D CMOS imagers, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 21, pp. 465–474, 2013.
2011
K. Fukuda, Sekitani, T., Yokota, T., Kuribara, K., Huang, T. - C. Jim, Sakurai, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic pseudo-CMOS circuits for low-voltage large-gain high-speed operation, Electron Device Letters, IEEE, vol. 32, pp. 1448–1450, 2011.
K. Fukuda, Sekitani, T., Yokota, T., Kuribara, K., Huang, T. - C. Jim, Sakurai, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic pseudo-CMOS circuits for low-voltage large-gain high-speed operation, Electron Device Letters, IEEE, vol. 32, pp. 1448–1450, 2011.
K. Fukuda, Sekitani, T., Yokota, T., Kuribara, K., Huang, T. - C. Jim, Sakurai, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic pseudo-CMOS circuits for low-voltage large-gain high-speed operation, Electron Device Letters, IEEE, vol. 32, pp. 1448–1450, 2011.
K. Fukuda, Huang, T. - C. Jim, Kuribara, K., Yokota, T., Sekitani, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic Pseudo-CMOS for 2V Operational High-Speed Circuits. 2011.
K. Fukuda, Huang, T. - C. Jim, Kuribara, K., Yokota, T., Sekitani, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic Pseudo-CMOS for 2V Operational High-Speed Circuits. 2011.
K. Fukuda, Huang, T. - C. Jim, Kuribara, K., Yokota, T., Sekitani, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic Pseudo-CMOS for 2V Operational High-Speed Circuits. 2011.
2010
M. Abbas, Cheng, K. - T. Tim, Furukawa, Y., Komatsu, S., and Asada, K., An Automatic Test Generation Framework for Digitally-assisted Adaptive Equalizers in High-speed Serial Links, in Proceedings of the Conference on Design, Automation and Test in Europe, 3001 Leuven, Belgium, Belgium, 2010.
H. - M. Sherman Chang, Huang, J. - L., Kwai, D. - M., Cheng, K. - T. Tim, and Wu, C. - W., An Error Tolerance Scheme for 3D CMOS Imagers, in Proceedings of the 47th Design Automation Conference, New York, NY, USA, 2010.
2005
K. Yang, Wang, L. - C., Cheng, K. - T. Tim, and Kundu, S., On statistical correlation based path selection for timing validation, in VLSI Design, Automation and Test, 2005.(VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on, 2005, pp. 8–11.
2002
A. Krstic, Lai, W. - C., Cheng, K. - T. Tim, Chen, L., and Dey, S., Embedded software-based self-testing for SoC design, in Proceedings of the 39th annual Design Automation Conference, 2002, pp. 355–360.