Biblio

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2014
D. Xiang, Sui, W., Yin, B., and Cheng, K. - T. Tim, Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 22, pp. 1968-1979, 2014.
2011
K. Fukuda, Sekitani, T., Yokota, T., Kuribara, K., Huang, T. - C. Jim, Sakurai, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic pseudo-CMOS circuits for low-voltage large-gain high-speed operation, Electron Device Letters, IEEE, vol. 32, pp. 1448–1450, 2011.
K. Fukuda, Sekitani, T., Yokota, T., Kuribara, K., Huang, T. - C. Jim, Sakurai, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic pseudo-CMOS circuits for low-voltage large-gain high-speed operation, Electron Device Letters, IEEE, vol. 32, pp. 1448–1450, 2011.
K. Fukuda, Huang, T. - C. Jim, Kuribara, K., Yokota, T., Sekitani, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic Pseudo-CMOS for 2V Operational High-Speed Circuits. 2011.
K. Fukuda, Huang, T. - C. Jim, Kuribara, K., Yokota, T., Sekitani, T., Zschieschang, U., Klauk, H., Ikeda, M., Kuwabara, H., Yamamoto, T., Takimiya, K., Cheng, K. - T. Tim, and Someya, T., Organic Pseudo-CMOS for 2V Operational High-Speed Circuits. 2011.
T. - C. Jim Huang, Fukuda, K., Lo, C. - M., Yeh, Y. - H., Sekitani, T., Someya, T., and Cheng, K. - T. Tim, Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics, Electron Devices, IEEE Transactions on, vol. 58, pp. 141-150, 2011.
2007
F. Zheng, Cheng, K. - T. Tim, Yan, X., Moondanos, J., and Hanna, Z., An efficient diagnostic test pattern generation framework using boolean satisfiability, in Asian Test Symposium, 2007. ATS'07. 16th, 2007.
K. Yang and Cheng, K. - T. Tim, Silicon Debug for Timing Errors, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 2084–2088, 2007.
2006
K. Yang and Cheng, K. - T. Tim, Efficient identification of multi-cycle false path, in Proceedings of the 2006 Asia and South Pacific Design Automation Conference, 2006, pp. 360–365.
Q. Zhu, Yeh, M. - C., and Cheng, K. - T. Tim, Multimodal fusion using learned text concepts for image categorization, in Proceedings of the 14th annual ACM international conference on Multimedia, 2006.
K. Yang and Cheng, K. - T. Tim, Timing-reasoning-based delay fault diagnosis, in Proceedings of the conference on Design, automation and test in Europe: Proceedings, 2006, pp. 418–423.
2005
Y. - C. Lin, Lu, F., Yang, K., and Cheng, K. - T. Tim, Constraint extraction for pseudo-functional scan-based delay testing, in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, 2005, pp. 166–171.
C. H. - P. Wen, Wang, L. - C., Cheng, K. - T. Tim, Yang, K., Liu, W. - T., Chen, J. - J., and , On a software-based self-test methodology and its application, in VLSI Test Symposium, 2005. Proceedings. 23rd IEEE, 2005, pp. 107–113.
K. Yang, Wang, L. - C., Cheng, K. - T. Tim, and Kundu, S., On statistical correlation based path selection for timing validation, in VLSI Design, Automation and Test, 2005.(VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on, 2005, pp. 8–11.