Embedded self-test for heterogeneous SoC
Yield and Cost Modeling of a Spare-Enhanced
Multi-core Chip
Resilient System Design, Task 1.2.3.4.
Saeed
Shamshiri and Kwang-Ting (Tim) Cheng
Abstract
It
becomes increasingly difficult to achieve a high manufacturing yield for
multi-core chips due to larger chip sizes, higher device densities, and greater
failure rates. By adding a limited number of spare cores to replace defective
cores either before shipment or in the field, the effective yield of the chip
and its overall cost can be significantly improved. Moreover, permanently
faulty wires of the network on chip can be replaced by spare wires.
In this project, we provide a yield and cost
analysis framework to better understand the dependency of a multi-core chip’s
cost on key parameters such as the number of spare cores and wires, yield,
shape parameter, scale parameter, and defect coverage of manufacturing and
in-field testing for each component of the chip. We apply our analysis on an
exemplary 9-core processor and on an Intel 80-core processor, and show that a
spare scheme can significantly improve the reliability, reduce the cost, and
substitute for the burn-in process. We also illustrate that, with in-field
recovery capability, the reliance on high quality manufacturing testing is
significantly reduced.
Publications
Two papers have been published on
this project so far. In the first paper, we have provided an analytical model
for the yield and cost of a multi-core system with spare cores. The analytical
results of this work show that the yield and cost of a multi-core system
improves significantly by integrating spare cores into the system. Furthermore, the burn-in process can be
eliminated and a cheaper manufacturing testing can be employed for more
reduction in the cost of such spare-enhanced system. In the second paper, we
consider communication in addition to computation for an NoC-based SoC with
mesh architecture. We model the yield and cost of a system with spare cores and
spare wires and show that the integrated redundancy in computation and
communication blocks makes the system more reliable and reduces the overall
cost.
1. Saeed Shamshiri, Peter Lisherness, Sung-Jui Pan, and Kwang-Ting Cheng, “A cost analysis framework for multi-core systems with spares,” in proc. of IEEE International Test Conference (ITC), Oct. 2008. [doc][pdf] [presentation]
2. Saeed Shamshiri and Kwang-Ting Cheng, “Yield and cost analysis of a reliable NoC,” to be appeared in VLSI Test Symposium (VTS), May 2009 [doc][pdf][presentation]
Posters
The first poster corresponds to the
first paper and the second poster corresponds to the second paper.
1. Saeed Shamshiri, Peter Lisherness, Sung-Jui Pan, and Kwang-Ting Cheng, “A cost analysis framework for multi-core systems with spares,” GSRC Annual symposium, Sep. 29-30, 2008. [ppt]
2. Saeed Shamshiri and Kwang-Ting Cheng, “Yield and Cost Modeling of a Spare-Enhanced NoC,” GSRC Quarterly Workshop, March 9-10, 2009. [ppt]
Technical Report
A complete set of models and
equations is available in this technical report:
1. S. Shamshiri and K.-T. Cheng, “Yield and cost analysis for spare-enhanced Network-on-Chips,” UCSB Technical Report, 2008. [pdf]
Demonstration Software
A software has been developed for
this project. The software covers the complete set of models and equations and
a
Demo program will be posted soon.
Last update: April 7, 2009