Embedded self-test for heterogeneous SoC  

Embedded software-base self-testing
Embedded software-based self-testing (SBST) becomes increasingly important as the cost of hardware testers continues to sky-rocket, supported on by decreasing feature sizes and increasing performance. Since cost is the major setback in the completeness of tests, more errors will be missed during testing. SBST, on the other hand, can use low-speed testers, run tests at full speed, and incur very little extra hardware costs, making it an attractive tool. Previous research on SBST has revolved around a microprocessor testing itself. We expand on this by studying the feasibility of using the microprocessor to test the rest of the system as well, using the IEEE P1500 Standard as an interface for test delivery. In our approach, we hope to apply test-generation for timing faults, providing SBST and speed-grading of the entire system.

Figure 1: Embedded Software-Based Self-Testing Flow

Publications:
• A. Krstic, L. Chen, W.-C. Lai, K.-T. Cheng, and S. Dey, Embedded Software-Based Self-Test for Programmable Core-Based Designs, IEEE Design and Test of Computers, Vol 19, 18-27, July, 2002.
• A. Krstic, W.-C. Lai, L. Chen, K.-T. Cheng, and S. Dey, Embedded Software-Based Self-Testing for SoC Design, Proc. 39th Design Automation Conf., New Orleans, LA, June 2002, pp. 355-360.
• W.-C. Lai and K.-T. Cheng, Instruction-Level DFT for Testing Processor and IP cores in System-on-a-Chip, Design Automation Conference, June, 2001.
• W.-C. Lai, J.-R. Huang and K.-T. Cheng, Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses, VLSI Test Symposium, April, 2001.
• W.-C. Lai, J.-R. Huang and K.-T. Cheng, Embedded Software-Based Approach to Testing Processor Cores and On-Chip Buses, Eighth International Test Synthesis Workshop, March 2001.
• W.-C. Lai, A. Krstic and K.-T. Cheng, Functionally Testable Path Delay Faults on a Microprocessor, Design & Test of Computers, pp. 6-14, Oct.-Dec. 2000.
• W.-C. Lai, A. Krstic and K.-T. Cheng, Test Program Synthesis for Path Delay Faults in Microprocessor Cores, Proceedings of International Test Conference, 2000.
• W.-C. Lai, A. Krstic, K.-T. Cheng, On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set,  Proceedings of IEEE VLSI Test Symposium, Montreal, Canada, May 2000.
• W.-C. Lai, A. Krstic and K.-T. Cheng, Self-Testing the Processor Cores for Delay Faults, Seventh International Test Synthesis Workshop, March 2000.
Online Checking
Online checking is a growing field, with circuits becoming more susceptible to transient faults (temporary faults caused by phenomena such as particle strikes or radiation). There are many on-line checking methodologies proposed today, yet there has not been a metric to compare them. We are developing methodologies for measuring the quality of on-line checking techniques, which use statistical means to diagnose the occurrence of a transient fault.