Embedded self-test for heterogeneous SoC  

Jitter Extraction and BER Testing for Multi-gigahertz Signals
 

Fig. 1
 
Goals
With the increasing demand for faster and faster communication systems, the data rate of some systems approaches multi-gigahertz range and even higher. In order to ensure the reliability of systems at such high frequency range, very expensive test equipment and a lot of test time are required. Thus, the conventional testing method is inadequate for high-volume production testing. The goal of this project is to develop effective methodologies to test these multi-gigahertz communication systems in a faster and cheaper way.
 
Description
Bit Error Rate (BER) is a widely used figure of merit to test a communication system. One of the major contributors to the BER is timing jitter, and another one is the characteristics of the receiver. This project focuses on developing a way of estimating the BER based on these parameters instead of applying ineffective conventional testing methods.
 
First, we propose an on-chip jitter spectral analysis technique that does not require expensive measuring equipment. The spectral information of the timing jitter for predicting the BER can be extracted using this technique. The timing jitter is defined as the deviation of a signal event from its ideal position, which is typically divided into 2 categories - Deterministic Jitter (DJ), and Random Jitter (RJ). To ensure reliable operation, extracting the type and amount of the  jitter is essential. However, most jitter-analysis techniques have centered on histogram-based analysis which conceals some of the important jitter information (Fig 2). In addition, any spectral analysis scheme requires accurate sampling and measuring equipment which is not easily available. The proposed technique obviates the need for this  expensive equipment.
 

Fig. 2
 
Second, the characteristics of the receiver should be considered for predicting the BER, specifically in the serial communication systems (e.g. PCI Express, SATA, SONET ). In these systems, the most important component of a receiver is a clock and data recovery (CDR) circuit, which extracts the clock signal from the data. The serial communication systems use the embedded clock scheme; the clock should be recovered at the receiver side. Since the quality of the recovered clock affects significantly the performance of the overall system, the transfer characteristic of the CDR circuit must be considered as well as the amount of jitter.
 
Publications:
• Chee-Kian Ong, Dongwoo Hong, Kwang_Ting(Tim) Cheng, Li-C Wang, "Technology-Portable On-chip Jitter Spectral Analysis Technique", VLSI Test Symposium, April 2004.
• Chee-Kian Ong, Dongwoo Hong, Kwang_Ting(Tim) Cheng, Li-C Wang, "Random Jitter Extraction Technique in a Multi-gigahertz Signal", Design, Automation & Test in Europe, February 2004.
• Chee-Kian Ong, Dongwoo Hong, Kwang_Ting(Tim) Cheng, Li-C Wang, "Jitter Spectral Extraction for Multi-gigahertz Signal", Asia and South Pacific Design Automation Conference, January 2004.