Statistical Delay Testing and Diagnosis
1. Noise-induced variability
Coupling capacitance, power grid fluctuation, leakage, and charge sharing - - - all pattern specific
2. Process induced variability
a. Spatial & temporal parametric variability: lot-to-lot, wafer-to-wafer, die-to-die
b. Limitations in lithography
c. CMP induced variability
Under delay variability, an efficient and effective timing analyzer is is required for building the foundation of delay testing and diagnosis. Our statistical timing analyzer uses a Monte-Carlo-based method to estimate the circuit delay under delay variability. Based on a pre-characterized cell-based delay library, this statistical timing analyzer can perform both static timing analysis (reporting the structural worst-case delay) and dynamic timing analysis (reporting the delay of each test pattern) on a design. This statistical-delay library reflects the timing effect of delay variability and represents the delay of each type of cell as a probability density function. Besides, our timing analyzer can also deal with the correlation between devices and hence is easier to apply advanced design issues such as cross-talk and power noise. Please visit our download page if you are interested in using our statistical timing analyzer.
• A. Krstic, J.-J. Liou, Y.-M. Jiang and K.-T. Cheng, "Delay Testing Considering Crosstalk-Induced Effects," in Proc. Int. Test Conf., pp. 558-567, Oct. 30-Nov. 1, 2001.
• J.-J. Liou, A. Krstic, Y.-M. Jiang and K.-T. Cheng, "Modeling, Testing, and Analysis for Delay Defects and Noise Effects in Deep Submicron Devices," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no.6, pp. 756-769, Jun. 2003.
In current industrial practice, critical path selection is an indispensable set for AC delay test and timing validation. We propose the concept and implementation of the universal path candidate set , which implies that testing all these paths can guarantee the actual circuit performance with very high probability. Using a universal path candidate set, our path-selection algorithm which select minimal required paths. The probabilistic information required in the path selection stage (i.e. the probabilities of being logically sensitizable, being timingly critical, and being timingly true) can be obtained from our statistical timing analysis tool. We also provide a theoretical upper bound for our path-selection algorithm.
• J.-J. Liou, L.-C. Wang and K.-T. Cheng, "On Theoretical and Practical Considerations of Path Selection for Delay Fault Testing," in Proc. Int. Conf. on Computer-Aided Design, pp. 94-100, Nov. 10-14, 2002.
• J.-J. Liou, A. Krstic, L.-C. Wang and K.-T. Cheng, "False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation," in Proc. Design Automation Conf., pp. 566-569, Jun. 10-14, 2002.
In the statistical timing domain, critical paths defined in a traditional discrete timing domain may not be critical in reality. Therefore we propose a statistical delay evaluation framework for evaluating the quality of a path set. In this new evaluation framework, we introduce a new objective function for path selection and demonstrate how the traditional definition of a critical path set may deviate from the true critical path set in statistical timing domain.
• J.-J. Liou, L.-C. Wang, A. Krstic, and K.-T. Cheng, "Experience in Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation,"in Proc. Asia and South Pacific Design Automation Conf., pp.751-756, Jan. 21-24, 2003.
For generating high quality tests for delay testing, we propose a SAT-based ATPG tool targeting a path-oriented transition fault model. Under this model, a transition fault is detected through the longest sensitizable path. Experiments with for this new fault model show higher test quality compared with other test sets: a single-detection transition-fault test set, a multiple-detection transition-fault test set, and a traditional critical-path test set added to the single-detection set. This ATPG tool can be orders-of-magnitude faster than a commercial ATPG tool.
In our ATPG stage, no timing information is involved. Hence after ATPG, we need a test selector to further maintain the test quality considering real timing information. For test selection, we propose a novel coverage metric to evaluating the test quality with respect to statistical timing defects under process variation. With this metric, we develop a test-selection algorithm to select minimal test patterns to achieve maximal test quality. Further, this metric can be used to predict the actual fail rate caused by statistical-timing defects for a given test.
• K. Yang, L.-C. Wang and K.-T. Cheng, "TranGen: A SAT-Based ATPG for Path-Oriented Transition Faults," Asia and South Pacific Design Automation Conf., Jan. 27-30, 2004.
• Mango C.-T. Chao, Li-C. Wang and Kwang-Ting Cheng, "Pattern Selection For Testing Of Deep Sub-Micron Timing Defects," Design, Automation & Test in Europe Conf., Feb 16-20, 2004.
The diagnosis problem for delay defects is fundamentally different from the diagnosis problem for logic defect (stuck-at faults), especially when we consider statistical timing models. First, the exact delay configuration of the failing chip instance is unknown. Second, even with the single defect assumption, the size of delay defects can be a random variable. For this new diagnosis problem, we introduce the concept of diagnosis error function, which operates on the probabilistic space, and then observe the performance of different error functions.
• A. Krstic, L.-C. Wang, K.-T. Cheng,J.-J. Liou, and M. S. Abadir, "Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step," in Proc. Design, Automation & Test in Europe, pp. 328-333, Mar. 3-7, 2003. [ Best Paper Award ]
• A. Krstic, L.-C. Wang, K.-T. Cheng and J.-J. Liou, "Diagnosis of Delay Defects Using Statistical Timing Models," in Proc. VLSI Test Symp., pp. 339-344, Apr. 27-May 1, 2003.