UCSB Statistical Timing Simulator - DSIM

- A Statistical TIming Simulation Tool -

When results are published using our tool, please refer to
Kai Yang, Kwang-Ting Cheng, Li-C. Wang, Jing-Jia Liou , "UCSB Statistical Timing Simulator - DSIM"

The proposed simulator has been applied in previous researches:

• "On The Development of A Statistical Timing Simulator for Timing Validation and Delay Testing"
  Kai Yang, Li-C. Wang, Kwang-Ting Cheng. ITSW 2004.

• "TranGen: A SAT-Based ATPG for Path-Oriented Transition Fault"
  Kai Yang, Kwang-Ting Cheng, Li-C. Wang. ASPDAC 2004.

The readme file is available Here.

The manual file (pdf) is available Here.

DSIM is a statistical timing simulator for combinational circuit implemented in C++.

This simulator is maintained by Kai Yang. The timing simulator algorithm is based on the single-stepping-transition-mode which assumes that when the first vector is applied, all circuit nodes have stabilized to their values under previous vector. To simulate the manufacturing process of K chips, we use the statistical simulator to produce K sample chip instances. Each sample instance has a different but fixed delay configuration. Given a set of patterns, the simulator performs timing simulation on each sample instance. Then, the simulator estimates the delay distribution for every pattern by aggregating the delay values achieved on these K chip instances. Statistics such as the average delay, the worst-case delay, the standard deviation can be computed for each pattern.

Our simulator takes the standard ".bench" format as inputs.

Thank you for your interest in this simulator

Kai Yang, PhD student, ECE, UCSB
kyang@ece.ucsb.edu

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