UCSB Circuit-SAT based Path-Delay-Fault ATPG - PathATPG

- An ATPG Tool -

When results are published using our tool, please refer to
"TranGen: A SAT-Based ATPG for Path-Oriented Transition Fault"
Kai Yang, Li-C. Wang, and Kwang-Ting Cheng,
Proc. ACM/IEEE ASP Design Automation Conference, 2004.

The proposed simulator has been applied in previous researches:

• "Timing-Reasoning-Based Delay Fault Diagnosis"
  Kai Yang, Kwang-Ting Cheng.
  Proceedings of Design Automation and Test in Europe, 2006.

• "On Statistical Correlation Based Path Selection for Timing Validation"
  Kai Yang, Li-C. Wang, Kwang-Ting Cheng.
  Proceedings of IEEE VLSI-TSA-DAT, 2005

• "Constraint Extraction for Pseudo-Functional Scan-based Delay Testing"
  Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Cheng.
  ACM/IEEE ASP Design Automation Conference, 2005.

• "On A Software-Based Self-Test Methodology and Its Application"
  Charles H.-P. Wen, L.-C. Wang, K.-T. Cheng, Kai Yang, and W.-T. Liu.
  Proceedings of IEEE VLSI Test Symposium, May 2005

• "On The Development of A Statistical Timing Simulator for Timing Validation and Delay Testing"
  Kai Yang, Li-C. Wang, Kwang-Ting Cheng. ITSW 2004.

• "TranGen: A SAT-Based ATPG for Path-Oriented Transition Fault"
  Kai Yang, Kwang-Ting Cheng, Li-C. Wang. ASPDAC 2004.

The readme file is available Here.

The manual file (pdf) is available Here.

PathATPG is a circuit-SAT based path-delay-fault ATPG for combinational and full-scan circuits implemented in C++.

This ATPG is maintained by Kai Yang.

Thank you for your interest in this ATPG

Kai Yang, PhD student, ECE, UCSB
kyang@ece.ucsb.edu

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