Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links

Submitted by Amirali Ghofrani on Tue, 04/07/2015 - 22:34

D. Hong and Cheng, K. - T. Tim, “Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links”, in VLSI Test Symposium, 2008. VTS 2008. 26th IEEE, 2008.