Skip to main content
UCSB SoC Design and Test Lab
Search form
Search
Main menu
Home
Members
Publications
Courses
Current Projects
You are here
Home
Test consideration for nanometer-scale CMOS circuits
Submitted by
superuser
on Mon, 04/06/2015 - 21:08
K. Roy
,
Mak, T. M.
, and
Cheng, K. - T. Tim
,
“
Test consideration for nanometer-scale CMOS circuits
”
,
Design & Test of Computers, IEEE
, vol. 23, pp. 128–136, 2006.
Google Scholar
BibTeX