Book and Chapter
A. Krstic and K.-T. Cheng, "Towards Testing Realistic Fault Behavior: Delay Fault Test," in Test Generation Technology for Digital Integrated Circuits: Foundations, Technology, Tools, H. T. Vierhaus and U. Glaeser, Eds.,  Springer, 1999, pp. 103-123. S.-Y. Huang and K.-T. Cheng, Formal Equivalence Checking and Design Debugging. Kluwer Academic Publishers, Boston, MA, 1998. A. Krstic and K.-T. Cheng, Delay Fault Testing for VLSI Circuits. Kluwer Academic Publishers, Boston, MA, 1998.
2009
Conference Paper  Saeed Shamshiri and Kwang-Ting (Tim) Cheng, " Yield and Cost Analysis of a Reliable NoC," in IEEE VLSI Test Symposium (VTS), pp. 173-178, May 2009. Hsiu-Ming (Sherman) Chang, Chin-Hsuan Chen, Kuan-Yu Lin, and Kwang-Ting (Tim) Cheng, " Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC," in IEEE VLSI Test Symposium (VTS), pp. 291-296, May 2009.
2008
Journal Article   T.-C. Huang and K.-T. Cheng, "Design for Low Power and Reliable Flexible Electronics: Self-Tunable Cell-Library Design," to appear in IEEE/OSA Journal of Display Technology (JDT) . C. Ong, D. Hong, K.-T. Cheng, and L. Wang, " A Clock-less Jitter Spectral Analysis Technique," in IEEE Transaction on Circuits and Systems, vol 55, no. 8, pp. 2263-2272, Sep. 2008. Tsung-Ching Huang, Huai-Yuan Tseng, Chen-Pang Kung, and Kwang-Ting Cheng, " Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si:H TFT Scan Driver," in ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 4, no. 3, article. 12, August 2008.      Conference Paper  Hsiu-Ming Chang, Min-Sheng Lin, and Kwang-Ting Cheng, " Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs," in IEEE Asian Test Symposium (ATS), pp. 43-48, Nov. 2008. Ming Gao, Hsiu-Ming Chang, Peter Lisherness, and Kwang-Ting Cheng, " Time-Multiplexed Online Checking: A Feasibility Study," in IEEE Asian Test Symposium (ATS), pp. 371-376, Nov. 2008. T.-C. Huang, Y.-H. Yeh, and K.-T. Cheng, " A 1.25KS/s 3-bit Flash ADC in a-Si:H TFTs for Flexible Sensors," in International Symposium for Flexible Electronics and Displays (ISFED), pp. 60-61, Nov. 13-14, 2008. Saeed Mirzaeian, Feijun (Frank) Zheng, and K.-T. Tim Cheng, " RTL Error Diagnosis Using a Word-Level SAT-Solver," in IEEE International Test Conference (ITC), Oct. 2008. Saeed Shamshiri, Peter Lisherness, Sung-Jui Pan, and Kwang-Ting Cheng, " A Cost Analysis Framework for Multi-core Systems with Spares," in IEEE International Test Conference (ITC), Oct. 2008. Dongwoo Hong and K.-T. Tim Cheng, " Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links," in IEEE VLSI Test Symposium (VTS), May 2008. [Best Paper Award]
2007
Journal Article   Kai Yang and K.-T. Cheng," Silicon Debug for Timing Errors," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, November 2007 Y.-C. Lin and K.-T. Cheng," Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 5, May 2007      Conference Paper  T.-C. Huang and K.-T. Cheng," Design for Printability for Flexible Electronics: Self-Tunable Cell Library Design," in International Symposium for Flexible Electronics and Displays (ISFED), Dec. 17-18, 2007. [Best Student Paper Award] Mango Chao, K.-T. Cheng, S. Wang, S. Chakradhar, and W. Wei," A Hybrid Scheme for Compacting Test Responses with Unknown Values," in IEEE Proc. International Conference on Computer-Aided Design (ICCAD), Nov. 2007. F. Zheng, K.-T. Cheng, X. Yan, J. Moondanos, and Z. Hanna," An Efficient Diagnostic Test Generation Framework Using Boolean Satisfiability," in IEEE Proc. Asian Test Symposium (ATS), Oct. 2007. D. Hong, and K.-T. Cheng," An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing," in IEEE Proc. Asian Test Symposium (ATS), Oct. 2007. T.-C. Huang, H.-Y. Tseng, C.-P. Kung, and K.-T. Cheng," Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si:H TFT Scan Driver," in IEEE Design Automation Conference (DAC), Jun. 4-8, 2007. F. Zheng, K.-T. Cheng, and X. Yan," An Enhanced Sequential ATPG Framework Based on Boolean Satisfiability," in 16th International Workshop on Logic & Synthesis (IWLS), May 2007. D. Hong, S. Saberi, K.-T. Cheng, and C.P. Yue," A Two-Tone Test Method for Continuous-Time Adaptive Equalizers," in IEEE Design, Automation and Test in Europe (DATE), Apr. 16-20, 2007. M. Lin, and K.-T. Cheng," Testable Design for Advanced Serial-Link Transceivers," in IEEE Design, Automation and Test in Europe (DATE), Apr. 16-20, 2007. S.-J. Pan, and K.-T. Cheng," A Framework for Reliability Analysis of System Fault Tolerance and Component Test Quality," in IEEE Design, Automation and Test in Europe (DATE), Apr. 16-20, 2007.
2006
Journal Article   D. Hong, C.-K. Ong, and K.-T. Cheng, " Bit-Error-Rate Estimation for High-Speed Serial Links, " in IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol.53, issue 12, pp. 2612-2627, Dec. 2006 Y.-C. Lin, F. Lu, and K.-T. Cheng," PseudoFunctional Testing," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.25, issue 8, pp.1535-1546, Aug. 2006 K. Roy, T. M. Mak, and K.-T. Cheng" Test Consideration for Nanometer-Scale CMOS Circuits," in IEEE  Design & Test of Computers, vol.23, no.2, pp.128-136, Mar. 2006      Conference Paper  F. Lu, and K.-T. Cheng, "IChecker: An Efficient Invariant Checker, " in IEEE High-Level Design Validation and Test Workshop, Nov. 9-10, 2006 D. Hong and K.-T. Cheng "Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links," in IEEE International Test Conference (ITC), Oct. 24-26, 2006. Y.-C. Lin and K.-T. Cheng, "A Unified Approach to Test Generation and Test Data Volume Reduction, " in IEEE International Test Conference (ITC), Oct. 24-26, 2006. Mitchell Lin and Tim Cheng, "Testable Design for Adaptive Linear Equalizer in High-Speed Serial Links," in IEEE International Test Conference (ITC), Oct. 24-26, 2006. M. C. -T. Chao, K.-T. Cheng, S. Wang, W.-L. Wei, "Unknown-Tolerance Analysis and Test-Quality Control for Test Response Compaction Using Space Compactors," in IEEE Design Automation Conference (DAC), Jul. 24-28, 2006. M. C. -T. Chao, K.-T. Cheng, S. Wang, W.-L. Wei, "Coverage Loss by Using Space Comactors in Presence of Unknown Values," in IEEE Design, Automation and Test in Europe (DATE), Mar. 6-10, 2006. Y.-C. Lin, F. Lu, and K.-T. Cheng, "Multiple-Fault Diagnosis Based on Single-Fault Activation and Single-Output Observation " in IEEE Proc. Design, Automation, and Test in Europe (DATE), Mar.6-10, 2006. Kai Yang, and K.-T. Cheng, "Timing-Reasoning-Based Delay Fault Diagnosis, " in IEEE Proc. Design, Automation, and Test in Europe (DATE), Mar. 6-10, 2006. Kai Yang, and K.-T. Cheng, "Efficient Identification of Multi-Cycle False Path, " in Proc. ACM/IEEE ASP Design Automation Conference (ASP-DAC) , Jan. 24-27, 2006. S.-J. Pan, K.-T. Cheng, J. Moondancs, and Z. Hanna, "Generation of Shorter Sequences for High Resolution Error Diagnosis Using Sequential SAT, " in Proc. ACM/IEEE ASP Design Automation Conference (ASP-DAC) , Jan. 24-27, 2006.
2005
Journal Article        Conference Paper  F. Lu, and K.-T. Cheng, "Sequential Equivalence Checking Based on K-th Invariants and Circuit SAT Solving, " in IEEE High-Level Design Validation and Test Workshop, Nov. 30 - Dec. 2, 2005 M. Lin, K.-T. Cheng, J. Hsu, M.-C. Sun, J. Chen, and S. Lu "Production-Oriented Interface Testing for PCI-Express by Enhanced Loop-Back Technique, "in IEEE Proc. Internatinal Testing Conference (ITC), pp. 78-80, Nov., 2005. M. C.-T. Chao, S. Wang, S.T. Chakradhar, and K.-T. Cheng, "Response Shaper: A Novel Technique to Enhance Unknown Tolerance for Output Response Compaction" in IEEE Proc. Internatinal Conference on Computer Aided Design (ICCAD), pp. 78-80, Nov. 6-10, 2005. G. Parthasarathy, M.K. Iyer, K.-T. Cheng, and F. Brewer, "RTL SAT Simplications by Boolean and Interval Arithmetic Reasoning," in IEEE Proc. Internatinal Conference on Computer Aided Design (ICCAD), pp. 297-302, Nov. 6-10, 2005. M. C.-T. Chao, S. Wang, S.T. Charkradhar, and K.-T. Cheng, "ChiYun Compact: A Novel Test Compaction Technique for Response with Unknown Values, " in IEEE Proc. Internatinal Conference on Computer Design (ICCD), pp. 147-152, Oct., 2005. Y.-C. Lin, F. Lu, and K.-T. Cheng, "Accurate Diagnosis of Multiple Faults" in IEEE Proc. Internatinal Conference on Computer Design (ICCD), pp. 153-156, Oct., 2005. G. Parthasarathy, M. K. Iyer, K.-T. Cheng, and Forrest Brewer, "Structural Search for RTL with Predicate Learning" in IEEE Proc. Design Automation Conference (DAC), pp. 451-456, June, 2005. Y.-C. Lin and K.-T. Cheng, "Pseudo-Functional Scan-based BIST for Delay Fault,"  in IEEE Proc. VLSI Test Symp.(VTS), pp.229 -234, May 1-5, 2005. C. H.-P. Wen, L.-C. Wang, K.-T. Cheng, Kai Yang, and W.-T. Liu, "On A Software-Based Self-Test Methodology and Its Application,"  in IEEE Proc. VLSI Test Symp.(VTS), pp.107 -113, May 1-5, 2005. D. Hong, C. Dryden, G. Saksena, and M. Panis, "An efficient Random Jitter Measurement Technique Using Fast Comparator Sampling,"  in IEEE Proc. VLSI Test Symp.(VTS), pp.123 -130, May 1-5, 2005. K. Yang, L.-C. Wang and K.-T. Cheng, "On Statistical Correlation Based Path Selection for Timing Validation," in IEEE VLSI-TSA International Symposium on VLSI Design, Automation, and Test, pp. -, Apr.27-29, 2005. F. Lu, M. K. Iyer, G. Parthasarathy and K.-T. Cheng, "An Efficient Sequential SAT Solver With Improved Search Strategies,"  in IEEE Proc. Design, Automation & Test in Europe (DATE), pp. 1102-1107, Mar. 7-11, 2005. M. K. Iyer, G. Parthasarathy and K.-T. Cheng, "Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver," in IEEE Proc. Design, Automation & Test in Europe (DATE), pp. 666-671, Mar. 7-11, 2005. Y.-C. Lin, F. Lu, K. Yang and K.-T. Cheng,, "Constraints Extraction for Pseudo-Functional Scan-based Delay Testing," to appear inIEEE Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), pp.166-171, Jan. 18-21, 2005
2004
Journal Article   F. Lu, L.-C. Wang, K.-T. Cheng, J. Moondanos and Z. Hanna, "A Signal Correlation Guided Circuit-SAT Solver," in Journal of Universal Computer Science, pp. 1629-1654, Dec, 2004 . J.-J. Liou, L.-C. Wang and  K.-T. Cheng, "Critical path selection for delay fault testing based upon a statistical timing model," IEEE Trans.  on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 11, pp. 1550-1560,  Nov.  2004. Y.-T. Chang and K.-T. Cheng, "Self-referential Verification for Gate-level Implementations of Arithmetic Circuits," IEEE Trans.  on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 7, pp. 1102-1112,  Jul.  2004. T.M. Mak, A. Krstic, K-T Cheng and L-C. Wang, "New Challenges in Delay Testing of Nanometer, Multigigahertz Designs,"IEEE Design & Test of Computers, vol. 21, no.3, pp. 241-247,  May./Jun.  2004. G. Parthasarathy, M. K. Iyer, K.-T. Cheng and  L.-C. Wang, "Safety Property Verification Using Sequential SAT and Bounded Model Checking," IEEE Design & Test of Computers, vol. , pp. 132-143,  Mar./Apr.  2004. C.K. Ong, K.-T. Cheng, and L. Wang, "A New Sigma-Delta Modulator Architecture for Testing Using Digital Stimulus," IEEE Trans. on Circuits and Systems, Part I, vol. 51, no.1, pp. 206-213, Jan. 2004.      Conference Paper  T. Feng, L.-C.Wang, K.-T. Cheng and Andy Lin, "On Using A 2-domain Partitioned OBDD Data Structure in Verification,"  in Proc. High-Level Design Validation and Test Workshop, pp.-, Nov. 10-14, 2004. M. C.-T. Chao, L.-C. Wang, T. Cheng and S. Kundu, "Static Statistical Timing Analysis for Latch-based Pipeline Designs," in Proc. Int. Conf. on Computer-Aided Design, pp. -, Nov. 7-11, 2004. D. Hong, C.-K. Ong, K.-T. Cheng, L Wang, "Bit Error Rate Estimation for High-Speed Serial Links Based on Sinusoidal and Random Jitters," in Proc. Int. Test Conf., pp. 1138-1147, Oct. 26-28, 2004. D. Hong, C.-K. Ong, K.-T. Cheng and L.-C. Wang, "Bit Error Rate Estimation for High-Speed Serial Links Based on Sinusoidal and Random Jitters," in Proc Int. Mixed-Signal Testing Workshop, pp. 41-50, Jun. 23-25, 2004. G. Parthasarathy, M. K. Iyer, K.-T. Cheng and L.-C. Wang, "An Efficient Finite Domain Constraint Solver for Circuits," in Proc. Design Automation Conf., pp. 212-217, Jun. 7-11, 2004. L.-C. Wang, T.M. Mak, K.-T. Cheng and M.S. Abadir, "On Path-Based Learning And Its Applications In Delay Test And Diagnosis," in Proc. Design Automation Conf., pp. 492-497, Jun. 7-11, 2004. C.-K. Ong, D. Hong, K.-T. Cheng, and L.-C. Wang, "A Scalable On-Chip Jitter Extraction Technique," in Proc. VLSI Test Symp., pp. 267-272, Apr. 25-29, 2004. T. Feng, L.-C. Wang, K.-T. Cheng, and A. C.-C Lin, "Improved symoblic simulation by dynamic funtional space partitioning," in Proc. Design, Automation & Test in Europe, pp. 42-47, Feb. 16-20, 2004. C.-K. Ong, D. Hong, K.-T. Cheng, and L.-C. Wang, "Random jitter extraction technique in a multi-gigahertz signal," in Proc. Design, Automation & Test in Europe, pp. 286-291, Feb. 16-20, 2004. M. C.-T. Chao, L.-C. Wang, and K.-T. Cheng, "Pattern selection for testing of deep sub-micron timing defects,"  in Proc. Design, Automation & Test in Europe, pp. 286-291, Feb. 16-20, 2004. K. Yang, K.-T. Cheng, and L.-C. Wang, "TranGen: A SAT-Based ATPG for Path-Oriented Transition Fault," in Proc. Asia and South Pacific Design Automation Conf., pp.92-97, Jan. 27-30, 2004. C.K. Ong, D. Hong, K.-T. Cheng, and L.-C. Wang, "Jitter Spectral Extraction for Multi-gigahertz Signal," in Proc. Asia and South Pacific Design Automation Conf., pp.298-303, Jan. 27-30, 2004. G. Parthasarathy, M. K. Iyer, K.-T. Cheng and L.-C. Wang, "Efficient Reachability Checking using Sequential SAT," in Proc. Asia and South Pacific Design Automation Conf., pp.418-423, Jan. 27-30, 2004. T. Feng, L.-C. Wang, and K.-T. Cheng, "Improved Symbolic Simulation By Functional-Space Decomposition," in Proc. Asia and South Pacific Design Automation Conf., pp.634-639, Jan. 27-30, 2004.
2003
Journal Article   J.-J. Liou, L.-C. Wang, A. Krstic, and  K.-T. Cheng, "Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, vol. E86-A, no. 12, Dec. 2003. H.-C. Hong, J.-L. Huang, K.-T. Cheng, C.-W. Wu and D.-M. Kwai, "Practical Considerations in Applying Sigma-Delta Modulation-Based Analog BIST to Sampled-Data Systems," IEEE Trans. on Circuits and Systems, Part II, vol. 50, no.9, pp. 553-566, Sep. 2003. A. Krstic, L.-C. Wang, K.-T. Cheng, J.-J. Liou, and M.S. Abadir, " Delay Defect Diagnosis Based Upon a Statistical Timing Model - The First Step, " in IEE Proc. Computers and Digital Techniques, vol.150, issue 5, pp. 346-354, Sep. 2006 L.-C. Wang, T. Feng, K.-T. Cheng, M. Abadir and M. Pandey, "Enhanced Symbolic Simulation For Functional Verification of Embedded Array Systems,"Kluwer Design Automation for Embedded Systems, Special Issue on Covalidation of Embedded Hardware/Software Systems, vol. 8, issue 2-3, pp. 173-188, Jun-Sep. 2003. J.-J. Liou, A. Krstic, Y.-M. Jiang and  K.-T. Cheng, "Modeling, Testing, and Analysis for Delay Defects and Noise Effects in Deep Submicron Devices," IEEE Trans.  on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 756-769,  Jun.  2003.      Conference Paper  G. Parthasarathy, M. K. Iyer, K.-T. Cheng, and L.-C. Wang, "A comparison of BDDs, BMC, and sequential SAT for model checking," in Proc. High-Level Design Validation and Test Workshop, pp.157-162, Nov. 12-14, 2003. A. Krstic, L.-C. Wang, K.-T. Cheng and T. M. Mak, "Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies," in Proc. Int. Test Conf., pp. 339-348, Sep. 30-Oct. 2, 2003. L.-C Wang, A. Krstic, L. Lee, K.-T. Cheng and M. Abadir, "Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects," in Proc. Int. Test Conf., pp. 1041-1050, Sep. 30-Oct. 2, 2003. F. Lu, L.-C. Wang, K.-T. Cheng, J. Moondanos and Z. Hanna, "A Signal Correlation Guided ATPG Solver and Its Applications for Solving Difficult Industrial Cases," in Proc. Design Automation Conf., pp. 668-673, Jun. 2-6, 2003. A. Krstic, L.-C. Wang, K.-T. Cheng, J.-J. Liou and T. M. Mak, "Enhancing Diagnosis Resolution for Delay Defects Based Upon Statistical Timing and Statistical Fault Models," in in Proc. Design Automation Conf., pp. 668-673, Jun. 2-6, 2003. C.-K. Ong, P.-W. Luo, Y.-J. Chang, K.-T. Cheng and W.-C. Wu, "DFT Sigma-Delta Modulator Architecture Implementation,¡¨ in Proc Int. Mixed-Signal Testing Workshop, pp. 137-142, June 25-27, 2003. C.-K. Ong, K.-T. Cheng and L.-C. Wang, "Delta-sigma Modulator Based Mixed-signal BIST Architecture for SoC," in Proc Int. Mixed-Signal Testing Workshop, pp. 669-674, June 25-27, 2003. K. Roy, T. M. Mak and K.-T. Cheng, "Test Consideration for Nanometer Scale CMOS Circuits," in Proc. VLSI Test Symp., pp. 313-315, Apr. 27-May 1, 2003. A. Krstic, L.-C. Wang, K.-T. Cheng and J.-J. Liou, "Diagnosis of Delay Defects Using Statistical Timing Models," in Proc. VLSI Test Symp., pp. 339-344, Apr. 27-May 1, 2003. A. Krstic, L.-C. Wang, K.-T. Cheng, J.-J. Liou, and M. S. Abadir, "Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step," in Proc. Design, Automation & Test in Europe, pp. 328-333, Mar. 3-7, 2003. [ Best Paper Award ] F. Lu, L.-C. Wang, K.-T. Cheng, R. C.-Y. Huang, "A Circuit SAT Solver with Signal Correlation Guided Learning," in Proc. Design, Automation & Test in Europe, pp. 892-897, Mar. 3-7, 2003. A. Krstic, J.-J. Liou, K.-T. Cheng and L.-C. Wang, "On Structural vs. Functional Testing for Delay Faults," in Proc. Int. Symp. on Quality Electronic Design, pp. 438-441, Mar. 24-26, 2003. M.K. Iyer, G. Parthasarathy and K.-T. Cheng, "SATORI--A Fast Sequential SAT Solver for Circuits," in Proc. Int. Conf. on Computer-Aided Design, pp. ,Nov. 9-13, 2003. T. Feng, Li-C. Wang, K.-T. Cheng, M. Pandey and M. S. Abadir, "Enhanced Symbolic Simulation for Efficient Verification of Embedded Array Systems," in Proc. Asia and South Pacific Design Automation Conf., pp.302-307, Jan. 21-24, 2003. C.-K. Ong, K.-T. Cheng and L.-C. Wang, "Delta-Sigma Modulator Based Mixed-Signal BIST Architecture for SoC," in Proc. Asia and South Pacific Design Automation Conf., pp.669-674, Jan. 21-24, 2003. J.-J. Liou, L.-C. Wang, A. Krstic, and  K.-T. Cheng, "Experience in Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation,"in Proc. Asia and South Pacific Design Automation Conf., pp.751-756, Jan. 21-24, 2003.
2002
Journal Article   A. Krstic, L. Chen, W.-C. Lai, K.-T. Cheng and  S. Dey, "Embedded Software-Based Self-Test for Programmable Core-Based Designs," IEEE Design & Test of Computers, vol. 19, pp. 18-27,  Jul.  2002.      Conference Paper    J.-J. Liou, L.-C. Wang and  K.-T. Cheng, "On Theoretical and Practical Considerations of Path Selection for Delay Fault Testing," in Proc. Int. Conf. on Computer-Aided Design, pp. 94-100, Nov. 10-14, 2002.   J.-J. Liou, L.-C. Wang, K.-T. Cheng, J. Dworak, M. R. Mercer, R. Kapur and T. W. Williams, "Analysis of Delay Effectiveness with a Multiple-Clock Scheme," in Proc. Int. Test Conf., pp. 408-416, Oct. 7-10, 2002. G. Parthasarathy, M. K. Iyer, T. Feng, L.-C. Wang, K.-T. Cheng and  M. S. Abadir, "Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems," in Proc. Int. Test Conf., pp. 203-212, Oct. 7-10, 2002. A. Krstic, W.-C. Lai, L. Chen, K.-T. Cheng, S. Dey,  "Embedded Software-Based Self-Testing for SoC Design," in Proc.  Design Automation Conf., pp. 335-360, Jun. 10-14, 2002. J.-J. Liou, L.-C. Wang, K.-T. Cheng, J. Dworak, M.R. Mercer, R. Kapur and T.W. Williams, "Enhancing Test Efficiency for Delay Fault Testing Using Multiple-Clocked Schemes," in Proc. Design Automation Conf., pp. 371-374, Jun. 10-14, 2002. J.-J. Liou, A. Krstic, L.-C. Wang and K.-T. Cheng, "False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation," in Proc. Design Automation Conf., pp. 566-569, Jun. 10-14, 2002. Y.-T. Chang and K.-T. Cheng, "Self-Referential Verification of Gate-Level Implementations of Arithmetic Circuits," in Proc.  Design Automation Conf., pp. 311-316, Jun. 10-14, 2002. M. K. Iyer, G. Parthasarathy, L.-C. Wang and K.-T. Cheng, "On the Development of an ATPG based Satisfiability Checker," in Proc. 3rd Microprocessor Test & Verification Workshop, pp. - , Jun. - , 2002. C.-K. Ong and K.-T. Cheng, "Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus," in Proc. VLSI Test Symp., pp. 123-128, Apr. 28-May 2, 2002. M. K. Iyer and K.-T. Cheng, "Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs," in Proc. VLSI Test Symp., pp. 139-144, Apr. 28-May 2, 2002.
2001
Journal Article   S.-Y. Huang, K.-T. Cheng and K.-C. Chen, "Verifying Sequential Equivalence Using ATPG Techniques," ACM Trans. on Design Automation of Electronic Systems, vol. 6, no.2, pp. 244-275, Apr. 2001. A. Krstic, Y.-M. Jiang and K.-T. Cheng, "Pattern Generation for Delay Testing and Dynamic Timing Analysis," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no.3, pp. 416-425,  Mar.  2001.       Conference Paper    G. Parthasarathy, C.-Y. Huang and K.-T. Cheng, "An analysis of ATPG and SAT algorithms for Formal Verification," in Proc. High-Level Design Validation and Test Workshop, pp.177-182, Nov. 7-9, 2001. Y.-T. Chang and K.-T. Cheng, "Induction-based Gate-Level Verification of Multipliers," in Proc. Int. Conf. on Computer-Aided Design, pp. 190-193, Nov. 4-8, 2001. A. Krstic, J.-J. Liou, Y.-M. Jiang and K.-T. Cheng, "Delay Testing Considering Crosstalk-Induced Effects," in Proc. Int. Test Conf., pp. 558-567, Oct. 30-Nov. 1, 2001. J.-J. Liou, K.-T. Cheng, S. Kundu and A. Krstic, "Fast Statistical Timing Analysis By Probabilistic Event Propagation," in Proc. Design Automation Conf., pp. 661-666, Jun. 18-22, 2001. W.-C. Lai and K.-T. Cheng, "Instruction-Level DFT for Testing Processor and IP cores in System-on-a-Chip," in Proc. Design Automation Conf., pp. 59-64, Jun. 18-22, 2001. C.-K. Ong, J.-L. Huang and K.-T. Cheng, "Testing second-order delta-sigma modulators using Pseudo-random Patterns," in Proc. Int. Mixed-Signal Testing Workshop, pp. - , Jun. 13-15, 2001 J.-L. Huang and K.-T. Cheng, "Characterization of a ADC/DAC Testing Technique for Built-In Self-Test Applications," in Proc. Int. Mixed-Signal Testing Workshop, pp. - , Jun. 13-15, 2001. W.-C. Lai, J.-R. Huang and K.-T. Cheng, "Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses," in Proc. VLSI Test Symp., pp. 204-209, Apr. 29-May 3, 2001. J.-L. Huang and K.-T. Cheng, "An on-chip short-time interval measurement technique for testing high-speed communication links," in Proc. VLSI Test Symp., pp. 380-385, Apr. 29-May 3, 2001.  J.-R Huang, .M. K. Iyer and K.-T. Cheng, "A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs," in Proc. VLSI Test Symp., pp. 198-203, Apr. 29-May 3, 2001.
2000
Journal Article   W.-C. Lai, A. Krstic and K.-T. Cheng, "Functionally Testable Path Delay Faults on a Microprocessor;" IEEE Design & Test of Computers, vol. 17, no.4, pp. 6-14, Oct.-Dec. 2000. J. -L. Huang and K.-T. Cheng, "Test Point Selection for Analog Fault Diagnosis on Unpowered Circuit Boards," IEEE Trans. on Circuits and Systems II, vol. 47, no. 10, pp. 977-987, Oct. 2000. A. Krstic, S. T. Chakradhar and K.-T. Cheng, "Testable Path Delay Fault Cover for Sequential Circuits," Jour.  on Information Science and Engineering, vol. 16, no. 5, pp. 673-686, Sept. 2000. S.-Y. Huang, K.-C. Chen, K.-T. Cheng, C.-Y. Huang and F. Brewer, "AQUILA: An Equivalence Checking System for Large Sequential Designs," IEEE Trans. on Computers, vol. 49, no.5, pp. 443-464, May 2000.. Y.-M. Jiang, A. Krstic, and K.-T. Cheng, "Estimation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 1, pp. 61-73, Feb. 2000.      Conference Paper     J.-J. Liou, Angela Kristic, Y.-M. Jiang and K.-T. Cheng, "Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects," in Proc. Int. Conf. on Computer-Aided Design, pp. 493-495, Nov. 5-9, 2000. J.-L. Huang and K.-T. Cheng, "Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis," in Proc. Int. Test Conf., pp. 1021-1030, Oct. 3-5, 2000. W.-C. Lai, A. Krstic and K.-T. Cheng, "Test Program Synthesis for Path Delay Faults in Microprocessor Cores,"  in Proc. Int. Test Conf., pp. 1080-1089, Oct. 3-5, 2000. J.L. Huang and K.-T. Cheng, "Testing and Characterization of the One-Bit First-Order Delta-Sigma Modulator for On-Chip Analog Signal Analysis," in Proc. Int. Mixed-Signal Testing Workshop, pp. - , Jun. 21-23, 2000. C.-Y. Huang and K.-T. Cheng, "Assertion Checking by Combined Word-level ATPG and Modular Arithmetic Constraint-Solving Techniques," in Proc. Design Automation Conf., pp. 118-123, Jun. 5-9, 2000. K.-T. Cheng, S. Dey, M. Rodgers and K. Roy, "Test Challenges for Deep Sub-Micron Technologies," in Proc. Design Automation Conf., pp. 142-149, Jun. 5-9, 2000. W.-C. Lai, A. Krstic and K.-T. Cheng, "On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set," in Proc. VLSI Test Symp., pp. 15-20, Apr. 30-May 4, 2000.  J.-J. Liou, K.-T. Cheng and D. Mukherjee, "Path Selection For Delay Testing of Deep Sub-micron Devices Using Statistical Performance Sensitivity Analysis," in Proc. VLSI Test Symp., pp. 97-104, Apr. 30-May 4, 2000.  J. A. Tofte, C.-K. Ong, J.-L. Huang and K.-T. Cheng, "Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-In-Self-Test," in Proc. VLSI Test Symp., pp. 237-246, Apr. 30-May 4, 2000. J.-L. Huang, C.-K. Ong, and K.-T. Cheng, "A BIST Scheme for On-Chip ADC and DAC Testing," in Proc. Design, Automation & Test in Europe, pp. 216-220, Mar. 27-30, 2000. Y.-M. Jiang, A. Krstic and K.-T. Cheng, "Dynamic Timing Analysis Considering Power Supply Noise Effects," in Proc. Int. Symp. on Quality of Electronic Design, pp. 137-143, Mar. 20-22, 2000. J.-J. Liou, A. Krstic, K.-T. Cheng, D. Mukherjee and S. Kundu, "Performance Sensitivity Analysis Using Statistical Methods and Its Applications to Delay Testing," in Proc. Asia and South Pacific Design Automation Conf., pp.587-592, Jan. 25-28, 2000. J.-L. Huang and K.-T. Cheng, "A Sigma-Delta Modulation Based BIST Scheme for Mixed-Signal Circuits," in Proc. Asia and South Pacific Design Automation Conf., pp.605-610, Jan. 25-28, 2000. H.-C. Tsai, K.-T. Cheng, and V. Agrawal, "A Testability Metric for Path Delay Faults and Its Application," in Proc. Asia and South Pacific Design Automation Conf., pp.593-598, Jan. 25-28, 2000.
1999
Journal Article   K.-T. Cheng and A. Krstic, "Current Directions in Automatic Test-Pattern Generation," IEEE Trans. on Computer, vol. 32, no. 11, pp. 58-64, Nov. 1999. K.-T. Cheng, S.-Y. Huang and W.-J. Dai, "Fault Emulation: A New Methodology for Fault Grading," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 10, pp. 1487-1495, Oct. 1999. S.-Y. Huang and K.-T. Cheng, "ErrorTracer: Design Error Diagnosis Based on Fault Simulation Techniques," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 9, pp. 1341-1352, Sept. 1999. S.-Y. Huang, K.-C. Chen and K.-T. Cheng, "AutoFix: A Hybrid Tool for Automatic Logic Rectification," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1376-1384, vol. 18, no. 9, pp. 1376-1384, Sept. 1999. H.-C. Tsai, K.-T. Cheng, and S. Bhawmik, "On Improving Test Quality of Scan-based BIST," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 8, pp. 928-938, Aug. 1999. A. Krstic, K.-T. Cheng and S. T. Chakradhar, "Primitive Delay Faults: Identification, Testing and Design for Testability," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 6, pp. 669-684, Jun. 1999. C.-Y. Pan and K.-T. Cheng, "Test Generation for Linear, Time-Invariant Analog Circuits and Its BIST Implementation,"  IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no.5, pp. 554-564, May 1999.      Conference Paper     C.-Y. Huang and K.-T. Cheng, "Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification Vectors," in Proc. Int. High Level Design Validation and Test Workshop, pp. - , Nov. 4-6, 1999. A. Krstic, Y.-M. Jiang and K.-T. Cheng, "Delay Testing Considering Power Supply Noise Effects," in Proc. Int. Test Conf., pp. 181-190, Sept. 28-30, 1999. Y.-M. Jiang, T. K. Young and K.-T. Cheng, "VIP - An Input Pattern Generator for Identifying Critical Voltage Drop for Deep Submicron Designs," in Proc. Int. Symp. on Low Power Electronics and Design, pp. 156-161, Aug. 16-17, 1999. Y.-M. Jiang and K.-T. Cheng, "Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices," in Proc. Design Automation Conf., pp. 760-765, Jun.  21-25, 1999. H.-C. Tsai, K.-T. Cheng and S. Bhawmik "Improving The Test Quality for Scan-based BIST Using A General Test Application Scheme," in Proc. Design Automation Conf., pp. 748-753, Jun.  21-25, 1999.  [ Best Paper Award ] A. Krstic, K.-T. Cheng and S. T. Chakradhar, "Testing High Speed VLSI Devices Using Slower Testers," in Proc. VLSI Test Symp., pp. 16-21, Apr. 25-29, 1999. J.-L. Huang, C.-Y. Pan, and K.-T. Cheng. "Specification Back-Propagation and Its Application to Fault Simulation of Analog/Mixed-Signal Circuits," in Proc. VLSI Test Symp., pp. 220-225, Apr. 25-29, 1999. Z. Yang, K.-T. Cheng and K.-L. Tai, "A New Bare Die Test Methodology," in Proc. VLSI Test Symp., pp. 290-295, Apr. 25-29, 1999.
~1998
Journal Article   H.-C. Tsai, K.-T. Cheng, C.-J. Lin and S. Bhawmik "Efficient Test Point Selection for Scan-based BIST," IEEE Trans. on  Very Large Scale Integration (VLSI) Systems, vol. 6, no.4, pp.667-676, Dec. 1998. A. Krstic and K.-T. Cheng, "Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability," Jour. Electronic Testing: Theory and Applications, vol. 11, pp. 43-54, Aug. 1997. K.-T. Cheng, A. Krstic and H.-C. Chen, "Generation of High Quality Tests for Robustly Untestable Path Delay Faults," IEEE Trans. on Computers, vol. 45, no. 12, pp. 1379-1392, Dec. 1996. K.-T. Cheng and H.-C. Chen, "Classification and Identification of Nonrobust Untestable Path Delay Faults," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 8, pp.845-853, Aug. 1996. K.-T. Cheng and A.S. Krishnakumar, "Automatic Functional Test Generation Using The Extended Finite State Machine Model," ACM Trans. on Design Automation of Electronic Systems, vol. 1, no.1, pp. 57-59, Jan. 1996. J.-Y. Jou and K.-T. Cheng, "Timing-Driven Partial Scan," IEEE Design and Test of Computers, vol. 12, no. 4, pp. 52-59, Winter 1995. K.-T. Cheng, "Single-Clock Partial Scan," IEEE Design and Test of Computers, vol. 12, no.2, pp. 24-31, Jun. 1995. L. A. Entrena and K.-T. Cheng, "Combinational and Sequential Logic Optimization by Redundancy Addition and Removal," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 7, pp. 909-916, Jul. 1995. T. J. Chakraborty, S. Davidson, F. Maamari and K.-T. Cheng, "Automatic Test Generation for Digital Electronic Circuits," AT&T Technical Journal, March/April 1994. Y.-M. Jiang, T.-F. Lee, T.-T. Hwang and Y.-L. Lin, "Performance-Driven Interconnection Optimization for Microarchitecture Design," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 2, pp. 137-149, Feb. 1994. K.-T. Cheng, "Transition Fault Testing For Sequential Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp.1971-1983, Dec. 1993. K.-T. Cheng and H.-K. T. Ma, "On the Over-Specification Problem In Sequential ATPG Algorithms," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 10, pp.1599-1604, Oct. 1993. K.-T. Cheng, S. Devadas and K. Keutzer, "Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 1, pp.13-24, August 1993. I. Pomeranz and K.-T. Cheng, "STOIC: State Assignment Based on Output/Input Functions," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 8, pp.1123-1231, Aug. 1993. K.-T. Cheng, "Redundancy Removal For Sequential Circuits Without A Reset States," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 1, pp.13-24, Jan. 1993.      Conference Paper    R. C.-Y. Huang and K.-T. Cheng, "A New Extended Finite State Machine (EFSM) Model for RTL Design Verification," in Proc. Int. High Level Design Validation and Test Workshop, pp. 47-53, Nov.  - , 1998. H.-C. Tsai, S. Bhawmik and K.-T. Cheng "An Almost Full-scan BIST Solution - Higher Fault Coverage and Shorter Test Application Time," in Proc. Int. Test Conf., pp. 1065-1073, Sept. 25-29, 1998. Y.-M. Jiang, K.-T. Cheng and A.-C. Deng, "Estimation of Maximum Power Supply Noise for Deep Sub-Micron Designs," in Proc. Int. Symp. on Low Power Electronics and Design, pp. 233-238, Aug. 10-12, 1998. S.-Y. Huang, K.-T. Cheng, K.-C. Chen and J.-Y. Lu, "Fault Simulation-Based Design Error Diagnosis for Sequential Circuits," in Proc. Design Automation Conf., pp. 632-637, Jun.  15-19, 1998. R. C.-Y. Huang, Y. Wang and K.-T. Cheng, "Libra-A Library-Independent Framework for Post-Layout Performance Optimization," in Proc. International Symp. on Physical Design, pp. 135-140, Apr. - , 1998. Y.-M. Jiang and K.-T. Cheng, "Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits," in Proc. Design, Automation & Test in Europe, pp. 698-702, Feb. 23-26, 1998. Y.-M. Jiang, S.-Y. Huang, K.-T. Cheng, D. Wang and C.-Y. Ho, "A Hybrid Power Model for RTL Power Estimation," in Proc. Asia and South Pacific Design Automation Conf., pp. 551-556, Feb. 10-13, 1998. A. Krstic, S. T. Chakradhar and K.-T. Cheng, "Design for Primitive Delay Fault Testability," in Proc. Int. Test Conf., pp. 436-445, Nov. 1-6, 1997. J.-L. Huang and K.T. Cheng, "Analog Fault Diagnosis for Unpowered Circuit Boards," in Proc. Int. Test Conf., pp. 640-648, Nov. 1-6, 1997. S.-Y. Huang, K.-T. Cheng, K.-C. Chen and D.-I. Cheng "ErrorTracer: A Fault Simulation-Based Approach to Design Error Diagnosis," in Proc. Int. Test Conf., pp. 974-981, Nov. 1-6, 1997. A. Krstic and K.-T. Cheng, "Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits," in Proc. Design Automation Conf., pp. 383-388, Jun 9-13, 1997. H.-C. Tsai, K.-T. Cheng, C.-J. Lin and S. Bhawmik "A Hybrid Algorithm for Test Point Selection for Scan-Based BIST," in Proc. Design Automation Conf., pp. 478-483, Jun. 9-13, 1997. Y.-M. Jiang, A. Krstic, K.-T. Cheng and M. Marek-Sadowska, "Post-Layout Logic Restructuring for Performance Optimization," in Proc. Design Automation Conf., pp. 662-665, Jun. 9-13, 1997. Y.-M. Jiang, K.-T. Cheng and A. Krstic, "Estimation of Maximum Power and Instantaneous Current Using a Genetic Algorithm," in Proc. Custom Integrated Circuits Conf., pp. 135-138, May 5-8, 1997. S.-Y. Huang, K.-C. Chen and K.-T. Cheng, "Incremental Logic Rectification," in Proc. VLSI Test Symp., pp. 144-149, Apr.  1997. C.-T. Chou, J.-L. Huang and M. Fujita, "A High-Level Language for Programming Complex Temporal Behaviors and Its Translation into Synchronous Circuits," in Proc. Int. Conf. on Computer Hardware Description Languages and their Applications, pp. 74-76, Apr. - , 1997. S.-Y. Huang, K.-T. Cheng and K.-C. Chen, "AQUILA: An Equivalence Verifier for Large Sequential Circuits," in Proc. Asia and South Pacific Design Automation Conf., pp. 455-460, Jan. 28-31, 1997. S.-Y. Huang, K.-C. Chen, K.-T. Cheng and T.-C. Lee, "Vector Generation for Accurate Power Simulation," in Proc. Design Automation Conf., pp. 161-164, Jun. 3-7 1996. S.-Y. Huang, K.-C. Chen and K.-T. Cheng, "Error Correction Based on Verification Techniques," in Proc. Design Automation Conf., pp. 258-261, Jun. 3-7 1996. A. Krstic, K.-T. Cheng and S. T. Chakradhar, "Identification and Test Generation for Primitive Faults," in Proc. Int. Test Conf., pp. 423-432, Oct. 20-25 1996. S.-Y. Huang, K.-T. Cheng, and K.-C. Chen, "An ATPG-based Framework for Verifying Sequential Equivalence," in Proc. Int. Test Conf., pp. 865-874, Oct. 20-25 1996. S.-Y. Huang, K.-T. Cheng and K.-C. Chen, "On Verifying the Correctness of Retimed Circuits," in Proc.Great-Lakes Symp. on VLSI, pp. 277-280, Mar. 22-23 1996. S.-Y. Huang, K.-T. Cheng, K.-C. Chen, and T.-C. Lee, "A Novel Methodology for Transistor-level Power Estimation," in Proc. Int. Symp. on Low Power Electronics and Designs, pp. 67-72, Aug. 12-14 1996. A. Krstic, S.T. Chakradhar and K.-T. Cheng, "Testable Path Delay Fault Cover for Sequential Circuits," in Proc. European Design Automation Conf., pp.220-226, Sept. 16-20 1996. A. Krstic and K.-T. Cheng, "Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability," in Proc. European Design and Test Conf., pp. 486-490, Mar. 11-14 1996. C.-Y. Pan and K.-T. Cheng, "Implicit Functional Testing for Analog Circuits," in Proc. VLSI Test Symp., pp. 489-494 , Apr. 28-May 1 1996. C.-Y. Pan and K.-T. Cheng, "Pseudo-Random Testing and Signature Analysis for Mixed-Signal Circuits," in Proc. Int. Conf. on Computer-Aided Design, pp. 102-107, Nov. 5-9 1995. K.-T. Cheng, S.-Y. Huang and W.-J. Dai, "Fault Emulation: A New Approach to Fault Grading," in Proc. Int. Conf. on Computer-Aided Design, pp. 681-686, Nov. 5-9 1995. C.-Y. Pan and K.-T. Cheng, "Pseudo-Random Testing for Mixed-Signal Circuits," in Proc. 2nd Int. Test Synthesis Workshop, pp. - , May - 1995. K.-T. Cheng, "Partial Scan Designs Without Using a Separate Scan Clock," in Proc. VLSI Test Symp., pp. 277-282, Apr 30-May 3 1995.. A. Krstic and K.-T. Cheng, "Generation of High Quality Tests for Functional Sensitizable Paths," in Proc. VLSI Test Symp., pp.374-379, Apr 30-May 3 1995. D. I. Cheng, M. Marek-Sadowska and K.-T.Cheng, "Speeding Up Power Estimation by Topological Analysis,"  in Proc. Custom Integrated Circuits Conf., pp. 623-626, May 1-4 1995. U. Sparmann, D Luxenburger, K.-T. Cheng and S. M. Reddy, "Fast Identification of Robust Dependent Path Delay Faults," in Proc. Design Automation Conf., pp. 119-125, Jun. 1995. S.-C.Chang, M.Marek-Sadowska and K.-T.Cheng "An Efficient Algorithm for Local Don't Care Set Calculation,"  in Proc. Design Automation Conf., pp. -, Jun. 1995. C. Lin, K.-C. Chen, S.-C.Chang, M.Marek-Sadowska and K.-T.Cheng, "Logic Synthesis for Engineering Change," in Proc. Design Automation Conf., pp. -, Jun. - 1995. U. Glaser and K.-T. Cheng, "Logic Optimization by an Improved Sequential Redundancy Addition and Removal Technique," in Proc. Asia and South Pacific Design Automation Conf., pp. 235-240, Aug. 29-Sept. 1 1995. K.-T. Cheng and C.-J. Lin, "Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST," in Proc. Int. Test Conf., pp. 506-514, Oct. 21-25 1995. K.-T. Cheng and Y.-S. Lin, "Minimax end-to-end delay routing and capacity assignment for virtual circuit networks," Proc. Global Telecommunications Conference, pp. 2134-2138, Dec. 13-17 1995. C.-Y. Pan, K.-T. Cheng and S. Gupta "A Comprehensive Fault Macromodel for Opamps," in Proc. Int. Conf. on Computer-Aided Design, pp.344-348, Nov. 6-10 1994. S.-C. Chang, K.-T. Cheng, N.-S. Woo and M. Marek-Sadowska, "Layout Driven Logic Synthesis for FPGAs," in Proc. Design Automation Conf., pp.  - ,Jun. - 1994.  [ Best Paper Award ] K.-T. Cheng and H.-C. Chen, "Generation of High Quality Non-Robust Tests for Path Delay Faults," in Proc. Design Automation Conf., pp. , Jun. - 1994. A. S. Krishnakumar and K.-T. Cheng, "On the Computation of the Set of Reachable States of Hybrid Models," in Proc. Design Automation Conf., pp -, Jun. -  1994. K.-T. Cheng and Y.-S. Lin, "On the Joint Virtual Path Assignment and Virtual Circuit Routing Problem in ATM Networks," in Proc. Global Telecommunications Conference, pp. 777-782, Nov. 28-Dec. 2 1994.