"Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing", Design Automation Conference (DAC), San Francisco, California, 06/2014.
"Joint Virtual Probe: Joint Exploration of Multiple Test Items’ Spatial Patterns for Efficient Silicon Characterization and Test Prediction", Design, Automation, and Test in Europe (DATE), Dresden, Germany, 03/2014.
"Thermal stress implications in athermal TiO2 waveguides on a silicon substrate", Optics Express, vol. 22, issue 1, pp. 661-666, 01/2014.
"Architecting Low Power Crossbar-Based Memristive RAM", Non-Volatile Memory Workshop , 03/2013.
"Coverage Discounting: Improved Testbench Qualification by Combining Mutation Analysis with Functional Coverage", SRC TechCon, Austin, TX, 09/2013.
"Digital-to-analog and analog-to-digital conversion with metal oxide memristors for ultra-low power computing", IEEE/ACM International Symposium on Nanoscale Architectures, New York City, USA, IEEE/ACM, 06/2013.
"Mutation Analysis with Coverage Discounting", Design, Automation Test in Europe Conference Exhibition (DATE), 2013, 03/2013.
"Test Data Analytics - Exploring Spatial and Test-Item Correlations in Production Test Data", International Test Conference (ITC), Anaheim, IEEE, 09/2013.
"Test-Quality Optimization for Variable n-Detections of Transition Faults", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, issue 99, 07/2013.
"Towards Data Reliable Crossbar-Based Memristive Memories", International Test Conference (ITC), Anaheim, IEEE, 09/2013.
"3D CMOS-Memristor Hybrid Circuits: Devices, Integration, Architecture, and Applications", IEEE International Symposium on Physical Design (ISPD), 03/2012.
"Adaptive Test Selection for Post-Silicon Timing Validation: A Data Mining Approach", IEEE 43rd International Test Conference (ITC), Anaheim, California, U. S. A., IEEE, 11/2012.
"Comprehensive Online Defect Diagnosis in On-Chip Networks", VLSI Test Symposium, 04/2012.
"On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation", The 17th Asia and South Pacific Design Automation Conference (ASP-DAC '12), Sydney, Australia , IEEE, ACM, 02/2012.
"Improving Validation Coverage Metrics to Account for Limited Observability", Asia and South Pacific Design Automation Conference, 02/2012.
"A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 04/2012.
"Post-Fabrication Reconfiguration for Power-Optimized Tuning of Optically Connected Multi-Core Systems", The 17th Asia and South Pacific Design Automation Conference (ASP-DAC '12), 02/2012.
"Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication", DATE'12: Design Automation and Test Europe, 03/2012.
"Power-Efficient Calibration and Reconfiguration for Optical Network-on-Chip", Journal of Optical Communications and Networking, vol. 4, issue 12, 12/2012.
"An all-digital built-in self-test technique for transfer function characterization of RF PLLs", Design, Automation Test in Europe Conference Exhibition (DATE), 2011, pp. 1 -6, 03/2011.
"Coverage Discounting: A Generalized Approach for Testbench Qualification", High Level Design Validation and Test Workshop, 2011. HLDVT 2011. IEEE International, 11/2011.
"End-to-end error correction and online diagnosis for on-chip networks", International Test Conference: IEEE, 09/2011.
"Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers", Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pp. 759 -764, 06/2011.
"Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip", Computers, IEEE Transactions on, vol. 60, no. 9, pp. 1246 -1259, 09/2011.
"Post-silicon bug detection for variation induced electrical bugs", 16th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 273 -278, 01/2011.