Publications

Export 270 results:
Author Title Type [ Year(Asc)]
2014
Feng, S., K. Shang, J. Bovington, R. Wu, K-T. Cheng, J. E. Bowers, and S.J.. Ben Yoo, "Athermal Characteristics of TiO2-Clad Silicon Waveguides at 1.3µm", IEEE Photonics Conference (IPC), San Diego, California, 10/2014. IPC2014.pdf (234.3 KB)
Rahimi, A., A. Ghofrani, M. Lastras, K-T. Cheng, R. Gupta, and L. Benini, "Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing", Design Automation Conference (DAC), San Francisco, California, 06/2014. DAC14.pdf (2.01 MB)
Lin, F., C-K. Hsu, and K-T. Cheng, "Feature Engineering with Canonical Analysis for Effective Statistical Tests Screening Test Escapes", International Test Conference (ITC), Seattle, Washington, 10/2014. ITC14.pdf (4.28 MB)
Zhang, S., F. Lin, C-K. Hsu, K-T. Cheng, and H. Wang, "Joint Virtual Probe: Joint Exploration of Multiple Test Items’ Spatial Patterns for Efficient Silicon Characterization and Test Prediction", Design, Automation, and Test in Europe (DATE), Dresden, Germany, 03/2014. DATE14.pdf (150.73 KB)
Lin, F., C-K. Hsu, and K-T. Cheng​, "Learning from Production Test Data: Correlation Exploration and Feature Engineering", Asian Test Symposium (ATS), Hangzhou, China, 11/2014. ATS14.pdf (2.46 MB)
Bovington, J., R. Wu, K-T. Cheng, and J. E. Bowers, "Thermal stress implications in athermal TiO2 waveguides on a silicon substrate", Optics Express, vol. 22, issue 1, pp. 661-666, 01/2014. OE14.pdf (1.08 MB)
2013
Lastras, M., A. Ghofrani, and K-T. Cheng, "Architecting Low Power Crossbar-Based Memristive RAM", Non-Volatile Memory Workshop , San Diego, California, 03/2013. NVMW13.pdf (721.83 KB)
Lesperance, N., P. Lisherness, and K-T. Cheng, "Coverage Discounting: Improved Testbench Qualification by Combining Mutation Analysis with Functional Coverage", SRC TechCon, Austin, Texas, 09/2013. TECHCON13.pdf (331.13 KB)
Gao, L., F. Merrikh-Bayat, X. Guo, D. B. Strukov, and K-T. Cheng, "Digital-to-analog and analog-to-digital conversion with metal oxide memristors for ultra-low power computing", IEEE/ACM International Symposium on Nanoscale Architectures, New York City, USA, IEEE/ACM, 06/2013. nanoarch2013.pdf (1.04 MB)
Lisherness, P., N. Lesperance, and K-T. Cheng, "Mutation Analysis with Coverage Discounting", Design, Automation Test in Europe Conference Exhibition (DATE), 2013, 03/2013. DATE13.pdf (167.64 KB)
Hsu, C-K., F. Lin, K-T. Cheng, W. Zhang, X. Li, J C. M. Jr., and K. M. Butler, "Test Data Analytics - Exploring Spatial and Test-Item Correlations in Production Test Data", International Test Conference (ITC), Anaheim, California, 09/2013. ITC13-2.pdf (1.39 MB)
Xu, D., H. Li, A. Ghofrani, K-T. Cheng, Y. Han, and X. Li, "Test-Quality Optimization for Variable n-Detections of Transition Faults", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, issue 99, 07/2013.
Ghofrani, A., M. Lastras, and K-T. Cheng, "Towards Data Reliable Crossbar-Based Memristive Memories", International Test Conference (ITC), Anaheim, California, 09/2013. ITC13.pdf (2.74 MB)
2012
Cheng, K-T., and D. Sturkov, "3D CMOS-Memristor Hybrid Circuits: Devices, Integration, Architecture, and Applications", IEEE International Symposium on Physical Design (ISPD), 03/2012. ispd71v-cheng_v2.pdf (936.34 KB)
Gao, M., P. Lisherness, and K-T(T). Cheng, "Adaptive Test Selection for Post-Silicon Timing Validation: A Data Mining Approach", IEEE 43rd International Test Conference (ITC), Anaheim, California, U. S. A., IEEE, 11/2012. ITC2012_AdaptiveTestSelection.pdf (2.13 MB)
Ghofrani, A., R. Parikh, S. Shamshiri, A. DeOrio, K-T(T). Cheng, and V. Bertacco, "Comprehensive Online Defect Diagnosis in On-Chip Networks", VLSI Test Symposium, 04/2012. VTS12_SRC.pdf (710.42 KB)
Gao, M., P. Lisherness, J-J. Liou, and K-T. Cheng, "On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation", The 17th Asia and South Pacific Design Automation Conference (ASP-DAC '12), Sydney, Australia , IEEE, ACM, 02/2012. ASPDAC2012_Glitch.pdf (795.44 KB)
Lisherness, P., and K-T. Cheng, "Improving Validation Coverage Metrics to Account for Limited Observability", Asia and South Pacific Design Automation Conference, 02/2012. ASPDAC_Invited.pdf (217.23 KB)
Chang, H-M(S)., J-L. Huang, D-M. Kwai, K-T. Cheng, and C-W. Wu, "A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 04/2012.
Zheng, Y., P. Lisherness, S. Shamshiri, A. Ghofrani, S. Yang, and K-T(T). Cheng, "Post-Fabrication Reconfiguration for Power-Optimized Tuning of Optically Connected Multi-Core Systems", The 17th Asia and South Pacific Design Automation Conference (ASP-DAC '12), 02/2012. ASPDAC2012_optical.pdf (221.18 KB)
Zheng, Y., P. Lisherness, M. Gao, J. Bovington, S. Yang, and K-T(T). Cheng, "Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication", DATE'12: Design Automation and Test Europe, 03/2012. DATE2012_Optical.pdf (341.67 KB)
Zheng, Y., P. Lisherness, M. Gao, J. Bovington, K-T. Cheng, H. Wang, and S. Yang, "Power-Efficient Calibration and Reconfiguration for Optical Network-on-Chip", Journal of Optical Communications and Networking, vol. 4, issue 12, 12/2012. JOCN_FinalResubmit_Yan.pdf (1.96 MB)
2011
Wang, P-Y., H-M(S). Chang, and K-T. Cheng, "An all-digital built-in self-test technique for transfer function characterization of RF PLLs", Design, Automation Test in Europe Conference Exhibition (DATE), 2011, pp. 1 -6, 03/2011. 2011_03_DATE2011_PLL_TF_BIST.pdf (383.78 KB)
Lisherness, P., and K-T. Cheng, "Coverage Discounting: A Generalized Approach for Testbench Qualification", High Level Design Validation and Test Workshop, 2011. HLDVT 2011. IEEE International, 11/2011. HLDVT11.pdf (167.75 KB)
Shamshiri, S., A. Ghofrani, and K-T. Cheng, "End-to-end error correction and online diagnosis for on-chip networks", International Test Conference: IEEE, 09/2011. 2011_ITC_Saeed.pdf (506.84 KB)

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