Publications

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2012
Ghofrani, A., R. Parikh, S. Shamshiri, A. DeOrio, K-T. Cheng, and V. Bertacco, "Comprehensive Online Defect Diagnosis in On-Chip Networks", VLSI Test Symposium, 04/2012.
Gao, M., P. Lisherness, J-J. Liou, and K-T. Cheng, "On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation", The 17th Asia and South Pacific Design Automation Conference (ASP-DAC '12), Sydney, Australia , IEEE, ACM, 02/2012. ASPDAC2012_Glitch.pdf (795.44 KB)
Lisherness, P., and K-T. Cheng, "Improving Validation Coverage Metrics to Account for Limited Observability", Asia and South Pacific Design Automation Conference, 02/2012. ASPDAC_Invited.pdf (217.23 KB)
Chang, H-M(S)., J-L. Huang, D-M. Kwai, K-T. Cheng, and C-W. Wu, "A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 04/2012.
Zheng, Y., P. Lisherness, S. Shamshiri, A. Ghofrani, S. Yang, and K-T(T). Cheng, "Post-Fabrication Reconfiguration for Power-Optimized Tuning of Optically Connected Multi-Core Systems", The 17th Asia and South Pacific Design Automation Conference (ASP-DAC '12), 02/2012. ASPDAC2012_optical.pdf (221.18 KB)
Zheng, Y., P. Lisherness, M. Gao, J. Bovington, S. Yang, and K-T(T). Cheng, "Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication", DATE'12: Design Automation and Test Europe, 03/2012. DATE2012_Optical.pdf (341.67 KB)
2011
Wang, P-Y., H-M(S). Chang, and K-T. Cheng, "An all-digital built-in self-test technique for transfer function characterization of RF PLLs", Design, Automation Test in Europe Conference Exhibition (DATE), 2011, pp. 1 -6, 03/2011. 2011_03_DATE2011_PLL_TF_BIST.pdf (383.78 KB)
Lisherness, P., and K-T. Cheng, "Coverage Discounting: A Generalized Approach for Testbench Qualification", High Level Design Validation and Test Workshop, 2011. HLDVT 2011. IEEE International, 11/2011. HLDVT11.pdf (167.75 KB)
Shamshiri, S., A. Ghofrani, and K-T. Cheng, "End-to-end error correction and online diagnosis for on-chip networks", International Test Conference: IEEE, 09/2011. 2011_ITC_Saeed.pdf (506.84 KB)
Chang, H-M(S)., and K-T. Cheng, "Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers", Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pp. 759 -764, 06/2011. 2011_06_DAC2011_ADCArraySpec.pdf (416.95 KB)
Shamshiri, S., and K-T. Cheng, "Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip", Computers, IEEE Transactions on, vol. 60, no. 9, pp. 1246 -1259, 09/2011. 2011_TC_Saeed.pdf (1.03 MB)
Gao, M., P. Lisherness, and K-T. Cheng, "Post-silicon bug detection for variation induced electrical bugs", 16th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 273 -278, 01/2011. Ming_ASP_DAC_2011_ElectricalBugModel.pdf (430.23 KB)
Huang, T-C., K. Fukuda, C-M. Lo, Y-H. Yeh, T. Sekitani, T. Someya, and K-T. Cheng, "Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics", Electron Devices, IEEE Transactions on, vol. 58, no. 1, pp. 141 -150, 01/2011. 10-TED-Huang-Pseudo-CMOS A Design Style for Low-Cost and Robust Flexible Electronics.pdf (1.44 MB)
Chang, H-M(S)., K-T. Cheng, W. Zhang, X. Li, and K. M. Bulter, "Test Cost Reduction Through Performance Prediction Using Virtual Probe", International Test Conference, Anaheim, California, U.S.A., IEEE, 09/2011. 2011_ITC_vp.pdf (411.34 KB)
Gao, M., H-M(S). Chang, P. Lisherness, and K-T. Cheng, "Time-Multiplexed Online Checking", Computers, IEEE Transactions on, vol. 60, no. 9, pp. 1300 -1312, 09/2011. 2011_09_TMOC.pdf (1.27 MB)
2010
Abbas, M., K-T. Cheng, Y. Furukawa, S. Komatsu, and K. Asada, "An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links", Design, Automation Test in Europe Conference Exhibition (DATE), 2010, pp. 1755 -1760, 03/2010.
Chang, H-M(S)., K-Y. Lin, and K-T. Cheng, "Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study", J. Electron. Test., vol. 26, Norwell, MA, USA, Kluwer Academic Publishers, pp. 59–71, 02/2010. 2010_02_JETTA_CalibrationTimeReduction.pdf (540.62 KB)
Chang, H-M(S)., K-Y. Lin, and K-T. Cheng, "Calibration-assisted production testing for digitally-calibrated ADCs", VLSI Test Symposium (VTS), 2010 28th, pp. 295 -300, 04/2010. Sherman_VTS2010.pdf (867.5 KB)
Gao, M., and K-T. Cheng, "A case study of Time-Multiplexed Assertion Checking for post-silicon debugging", High Level Design Validation and Test Workshop (HLDVT), 2010 IEEE International, pp. 90 -96, 06/2010. Ming_HLDVT.pdf (685.54 KB)
Cheng, K-T., and T-C. Huang, "Design, analysis, and test of low-power and reliable flexible electronics", VLSI Test Symposium (VTS), 2010 28th, pp. 82, 04/2010. Tim_Jim_VTS2010.pdf (650.97 KB)
Hong, D., and K-T. Cheng, Efficient test methodologies for high-speed serial links, , vol. 51: Springer Verlag, 2010.
Chang, H-M(S)., J-L. Huang, D-M. Kwai, K-T. Cheng, and C-W. Wu, "An error tolerance scheme for 3D CMOS imagers", Design Automation Conference (DAC), 2010 47th ACM/IEEE, pp. 917 -922, 06/2010. 2010_06_DAC2010_Sherman_ET3DImager.pdf (1.8 MB)
Shamshiri, S., and K-T. Cheng, "Error-locality-aware linear coding to correct multi-bit upsets in SRAMs", Test Conference (ITC), 2010 IEEE International, pp. 1 -10, 11/2010. saeed_shamshiri_ITC10_paper7.1.pdf (450.18 KB)
Chang, H-M(S)., and K-T. Cheng, "Low-cost quality assurance techniques for high-performance mixed-signal/RF circuits and systems", Test Conference (ITC), 2010 IEEE International, pp. 1 -10, 11/2010. 2010_11_ITC2010_Sherman_QualityAssuranceTechniques.pdf (1.46 MB)
Shamshiri, S., and K-T. Cheng, "Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy", VLSI Test Symposium (VTS), 2010 28th, pp. 194 -199, 04/2010. saeed_shamshiri_VTS10_6b1.pdf (1.08 MB)

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