K.-T. Tim Cheng
Primary tabs
] , “A low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory”, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 12, no. 1, 2015.
JETC15.pdf (3.27 MB)
JETC15.pdf (3.27 MB), “Pairwise Proximity-Based Features for Test Escape Screening”, in International Conference on Computer-Aided Design (ICCAD), Austin, TX, 2015. iccad15.pdf (792.61 KB)
iccad15.pdf (792.61 KB), “Toward Large-Scale Access-Transistor-Free Memristive Crossbars”, in Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific, 2015. ASPDAC_invited.pdf (3.38 MB)
ASPDAC_invited.pdf (3.38 MB), “Variation-Aware Adaptive Tuning for Nanophotonic Interconnects”, in International Conference on Computer-Aided Design (ICCAD), Austin, TX, 2015. ICCAD2015_IEEE.pdf (967.71 KB)
ICCAD2015_IEEE.pdf (967.71 KB), “Vertical Integration of Memristors onto Foundry CMOS Dies using Wafer-Scale Integration”, in IEEE Electronic Components and Technology Conference (ECTC’15), San Diego, USA, 2015. ECTC15.pdf (378.91 KB)
ECTC15.pdf (378.91 KB), “Athermal characteristics of TiO2-clad silicon waveguides at 1.3 um”, in Photonics Conference (IPC), IEEE, San Diego, CA, 2014. IPC2014_submit.pdf (213.72 KB)
IPC2014_submit.pdf (213.72 KB), “Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 22, pp. 1968-1979, 2014.
, “Energy-efficient GPGPU architectures via collaborative compilation and memristive memory-based computing”, in Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE, 2014. DAC14-memristor.pdf (1.69 MB)
DAC14-memristor.pdf (1.69 MB), “Feature engineering with canonical analysis for effective statistical tests screening test escapes”, in Test Conference (ITC), 2014 IEEE International, 2014. itc14.pdf (4.28 MB)
itc14.pdf (4.28 MB), “Joint Virtual Probe: Joint exploration of multiple test items' spatial patterns for efficient silicon characterization and test prediction”, in Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, 2014.
, “Learning from Production Test Data: Correlation Exploration and Feature Engineering”, in Test Symposium (ATS), 2014 IEEE 23rd Asian, 2014. ats14.pdf (2.45 MB)
ats14.pdf (2.45 MB), “Test-Quality Optimization for Variable n -Detections of Transition Faults”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 22, pp. 1738-1749, 2014.
, “Thermal stress implications in athermal TiO2 waveguides on a silicon substrate”, Optics Express, vol. 22, no. 1, pp. 661–666, 2014. OE14.pdf (1.08 MB)
OE14.pdf (1.08 MB), “Architecting Low Power Crossbar-Based Memristive RAM”, in Non-Volatile Memory Workshop, San Diego, USA, 2013. NVMW13.pdf (721.83 KB)
NVMW13.pdf (721.83 KB), “Digital-to-analog and analog-to-digital conversion with metal oxide memristors for ultra-low power computing”, in Nanoscale Architectures (NANOARCH), 2013 IEEE/ACM International Symposium on, 2013.
, “Low-cost error tolerance scheme for 3-D CMOS imagers”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 21, pp. 465–474, 2013.
, “Mutation analysis with coverage discounting”, in Design, Automation Test in Europe Conference (DATE), 2013. DATE13.pdf (167.64 KB)
DATE13.pdf (167.64 KB), “Role of thermal stress in athermal waveguide design using TiO2 waveguides on a silicon substrate”, in Photonics Conference (IPC), IEEE, Seattle, WA, 2013. IPC_2013_final.pdf (215.82 KB)
IPC_2013_final.pdf (215.82 KB), “Test data analytics - Exploring spatial and test-item correlations in production test data”, in Test Conference (ITC), 2013 IEEE International, 2013.
, “Towards data reliable crossbar-based memristive memories”, in Test Conference (ITC), 2013 IEEE International, 2013. ITC'13_CR.pdf (2.68 MB)
ITC'13_CR.pdf (2.68 MB), “3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications”, in Proceedings of the 2012 ACM International Symposium on Physical Design, 2012.
, “Adaptive test selection for post-silicon timing validation: A data mining approach”, in Test Conference (ITC), 2012 IEEE International, 2012.
, “Comprehensive online defect diagnosis in on-chip networks.”, in VLSI Test Symposium (VTS), 2012. VTS12_cr.pdf (710.92 KB)
VTS12_cr.pdf (710.92 KB), “On error modeling of electrical bugs for post-silicon timing validation”, in Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 2012.
, “Improving validation coverage metrics to account for limited observability”, in Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 2012.