K.-T. Tim Cheng

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T. - C. Jim Huang and Cheng, K. - T. Tim, Design for Printability for Flexible Electronics: Self-Tunable Cell-Library Design, in International Symposium for Flexible Electronics and Displays (ISFED), Hsinchu, Taiwan, 2007.
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M. C. - T. Chao, Cheng, K. - T. Tim, Wang, S., Chakradhar, S. T., and Wei, W. - L., A hybrid scheme for compacting test responses with unknown values, in Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007.
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Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Multiple-fault diagnosis based on adaptive diagnostic test pattern generation, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 932–942, 2007.
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K. Yang and Cheng, K. - T. Tim, Silicon Debug for Timing Errors, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 2084–2088, 2007.
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M. Lin and Cheng, K. - T. Tim, Testable design for advanced serial-link transceivers, in Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE'07, 2007.
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K. - T. Tim Cheng, Automatic Test Pattern Generation, in EDA for IC System Design, Verification, and Testing, CRC Press, 2006.
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D. Hong and Cheng, K. - T. Tim, Bit error rate estimation for improving jitter testing of high-speed serial links, in Test Conference, 2006. ITC'06. IEEE International, 2006.
D. Hong, Ong, C. - K., and Cheng, K. - T. Tim, Bit-error-rate estimation for high-speed serial links, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 53, pp. 2616–2627, 2006.
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M. C. - T. Chao, Wang, S., Chakradhar, S. T., Wei, W., and Cheng, K. - T. Tim, Coverage loss by using space compactors in presence of unknown values, in Proceedings of the conference on Design, automation and test in Europe: Proceedings, 2006, pp. 1053–1054.
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K. Yang and Cheng, K. - T. Tim, Efficient identification of multi-cycle false path, in Proceedings of the 2006 Asia and South Pacific Design Automation Conference, 2006, pp. 360–365.
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S. - J. Pan, Cheng, K. - T. Tim, Moondanos, J., and Hanna, Z., Generation of shorter sequences for high resolution error diagnosis using sequential sat, in Proceedings of the 2006 Asia and South Pacific Design Automation Conference, 2006, pp. 25–29.
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F. Lu and Cheng, K. - T. Tim, IChecker: An efficient checker for inductive invariants, in High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International, 2006.
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Q. Zhu, Yeh, M. - C., and Cheng, K. - T. Tim, Multimodal fusion using learned text concepts for image categorization, in Proceedings of the 14th annual ACM international conference on Multimedia, 2006.
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Y. - C. Lin and Cheng, K. - T. Tim, Multiple-fault diagnosis based on single-fault activation and single-output observation, in Design, Automation and Test in Europe, 2006. DATE'06. Proceedings, 2006, vol. 1, pp. 1–6.
Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Pseudofunctional testing, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 1535–1546, 2006.
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K. Roy, Mak, T. M., and Cheng, K. - T. Tim, Test consideration for nanometer-scale CMOS circuits, Design & Test of Computers, IEEE, vol. 23, pp. 128–136, 2006.
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K. Yang and Cheng, K. - T. Tim, Timing-reasoning-based delay fault diagnosis, in Proceedings of the conference on Design, automation and test in Europe: Proceedings, 2006, pp. 418–423.
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Y. - C. Lin, Lu, F., and Cheng, K. - T. Tim, Accurate diagnosis of multiple faults, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 153–156.
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M. C. - T. Chao, Wang, S., Chakradhar, S. T., and Cheng, K. - T. Tim, ChiYun compact: a novel test compaction technique for responses with unknown values, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 147–152.

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