********************************************************************************* *** Demo Name: Time-Multiplexed Online Checking *** Presented by: UCSB Design and Test Lab *** Release Time: For GSRC Annual Review, 2008.09.29-30 *** Platform: XUP V2P-30 *** Design Driver: Xilinx XUP Video Capture Reference Design *** Contact: "Ming Gao" *** ********************************************************************************* INDEX 1. Preliminary 2. Setup 3. Demonstration 1. Preliminary 1.1. Time-Multiplexed Online Checking (TMOC) As semiconductor technology progress toward nano-scale, increasing design complexity as well as costly production testing and burn-in make it more difficult to ensure the shipment of failure-free chips. Additional in-field failure sources such as infant mortality, soft errors, silicon aging, and electro-migration contribute to quality degradation as well. To increase in-field chip availability, online checking followed by a fault circumvention process could be a promising direction. Such a solution would result in a lower product return rate and service cost. The area overhead and performance penalties of existing online checking approaches are very significant. Thus, these online checking solutions would not be suitable for cost-sensitive applications such as most consumer electronics. To reduce hardware overhead, we propose an online checking scheme "Time-Multiplexed Online Checking (TMOC)[1]" that offers sufficient fault coverage with less overhead at the cost of increased fault detection latency. In TMOC, a design is partitioned into modules, each of which has its own TMOC checker. One or more embedded, field-reprogrammable blocks are used as shared checker spaces. Several TMOC checkers for different modules are sequentially and periodically mapped into a shared field-reprogrammable checker space in a time interleaved fashion. TMOC can be applied to systems that can tolerate a certain level of fault detection latency and that implemented either solely in FPGA or in SoC/SiP with an embedded field-reprogrammable block. We have successfully implemented this TMOC scheme on a set of arithmetic circuits and Finite State Machines (FSMs) without disturbing system operations on a Virtex II Pro board. A case study on a JPEG codec design and a demonstration based on a TV-to-VGA decoder demonstrated the feasibility of applying TMOC to complex designs by employing the proposed state synchronization technique. The experiment results showed that a significant checker area overhead reduction can be achieved when the design is properly partitioned. Reference: [1] Ming Gao, Hsiu-Ming Chang, Peter Lisherness, and Kwang-Ting Cheng, "Time-Multiplexed Online Checking: A Feasibility Study," to appear in Proceedings of the 17th Asian Test Symposium (November 24 - 27, 2008). ATS. IEEE Computer Society, Sapporo, Japan. 1.2 Design Driver Xilinx XUP-V2P Reference Design: Video Decoder using VDEC-1 The XUPV2P Development System when equipped with a VDEC1 Video decoder uses an Analog Devices ADV7183B to sample the incoming analog video and convert it to digital values according to the video standards ITU-R.656 and ITU-R BT.601. In this example design, the video is then further converted to be displayed on a standard VGA display as progressive video output on the XUP boardĄ¯s SVGA port. More details about the reference design go to: http://www.xilinx.com/univ/xupv2p_demo_ref_designs.htm In this demo, we modified the design to accommodate PAL_D standard and set S-Video as the only video source port. In order to demonstrate TMOC scheme, we implemented TMOC to three existing design modules using one checker space. Module 1 = Line Field Decoder [49 slices] Module 2 = 422 to 444 Converter [51 slices] Module 3 = Timing Generation Logic [47 slices] 1.3 Hardware/Software List 1.3.1 Hardware List XUP-V2P-30 Platform Board VDEC1 Video Capture Doughter Card (connect to XUP-V2P board via I2C; J1 jumps to logic0) Board Power (for XUP-V2P board) Xilinx USB Program Cable (connect XUP-V2P board to control host PC) CF card and reader (copy ACE/Bit files to CF and insert CF to ACE slot of XUP-V2P) S-video Cable (connect between Laptop/DVD player to VDEC1 daughter card) 9-pin Straight-Through RS232 cable (connect between XUP-V2P to control host PC) 1.3.2 EDA Tools List ISE 9.1i SP2 with PlanAhead Early Access patch EDK 9.1i PlanAhead 9.2.5 1.3.3 Executable File List system.ace a.bit b.bit c.bit blank.bit executable.elf 1.3.4 CF Re-image Tools List Either follow the instruction of ... http://china.xilinx.com/products/boards/ml405/docs/ml405_cf_reimage.pdf Or simply use "mkdosfs -v -F 16 " 2. Setup 2.1 Connections Step 1: Connect the VDEC1 daughter board to XUP-V2P board via I2C bus interface. Step 2: Connect the Xilinx USB Cable to XUP-V2P board and control host PC. Step 3: Connect the 9-pin straight-through serial cable to XUP-V2P and host PC. Step 4: Connect s-video cable to VDEC1 board and video source (laptop/DVD player/TV) Step 5: Connect VGA output of XUP V2P board to a VGA compatible LCD/CRT. Step 6: Connect XUP-V2P board to power strip. 2.2 Configurations Note: system.ace = static_full.bit + a.bit + executable_debug.elf Automatically Partial Reconfiguration operated by PPC405_0 Step 1: Format/Re-image your CF card to FAT16. Step 2: Copy system.ace to the root directory of your CF card. Step 3: Copy a/b/c/blank.bit to the root directory of CF card. Step 4: Insert CF card to ACE slot and configure a hyperterminal with 9600-N-1-N. Step 5: Turn on XUP-V2P board, and you should be able to see VGA output on your LCD, and also operation menu of executalbe_debug.elf on hyperterminal window. Step 6: Lunch XPS and XMD, "dow executable.elf" and "con". You should be able to see a new operation menu of executable.elf promoted from hyperterminal window. Manually Partial Reconfiguration operated by PPC405_0 Step 1: Format/Re-image your CF card to FAT16. Step 2: Copy system.ace to the root directory of your CF card. Step 3: Insert CF card to ACE slot and configure a hyperterminal with 9600-N-1-N. Step 4: Turn on XUP-V2P board, and you should be able to see VGA output on your LCD, and also operation menu of executalbe_debug.elf on hyperterminal window. Step 5: Lunch iMPACT and initialize JTAG chain. Download a/b/c/blank.bit accordingly. 3. Demonstration ********************************************************* <<< Time-Multiplexed Online Checking (TMOC) Demo >>> -== UCSB SoC Design and Test Lab ==- (GSRC Annual Symposium, 2008.09) ---------------------------------------------------------- Operation Menu ---------------------------------------------------------- 1 - Connect Checker to Module 1. 2 - Connect Checker to Module 2. 3 - Connect Checker to Module 3. d - Disconnect Checker to Design. i - Inject a fault to Module 1 and connect checker to Module 1. j - Inject a fault to Module 1 and connect checker to Module 2. n - Inject a fault to Module 1 and connect checker to Module 3. k - Inject a fault to Module 3 and connect checker to Module 3. h - Inject a fault to Module 3 and connect checker to Module 2. m - Inject a fault to Module 3 and connect checker to Module 1. r - Recover the system operation and disconnect checker to design. q - Quit ************************************************************** 3.1 TMOC does not interrupt system operation Operation Sequence: 1,2,3,2,3,2,3.... Observation: No interruption on VGA output during TMOC (Partial Reconfiguration) A Known Issue: When "checker 1" is downloaded again to the checker space, the detection LED will be lighted even if there is no fault injected. This is due to an implementation flaw of the system.ace file. When downloading "checker 1" manually through Xilinx iMPACT tool, this issue should disappear. 3.2 State-Flush works and does not incur much time overhead Operation Sequence: 1,2,3,2,3,2,3.... Observation: Watch the "detection LED"; Both PR and Synchronization can be completed in 10's to 100's milliseconds. 3.3 Fault Injection and Detection on datapath Operation Sequence: reboot system, 1,i,j,n,i,r Observation: Watch the "detection LED"; No fault detection at the very beginning; Fault detected and VGA output failed as soon as fault injected; No fault detected during checking module 2 and 3; Fault detected again when checking module 1; Triggering recovery procedure and VGA output gets back to normal mode. 3.4 Fault Injection and Detection on control signal Operation Sequence: reboot system, 3,k,h,m,k,r Observation: Watch the "detection LED"; No fault detection at the very beginning; "Detection LED" blinks and VGA output failed as soon as fault injected; No fault detected during checking module 1 and 2; Fault detected again when checking module 3; Triggering recovery procedure and VGA output gets back to normal mode. Note: When the fault in module 3 is detected, the LED is blinking because the data stream may not constantly manifest this fault. This is due to the inherent nature of online checking. In other words, even if a dedicated online checker is implemented (i.e. no TMOC), the LED will be blinking too. However, it might seems conflict that the screen stuck at dark even when the fault was not manifested(LED was on). This is because the fault was injected on the VGA horizontal synchronization signal. The time required for recovering from the faulty (Asynchronized) state is much longer than the gap between two successive fault manifestations. Therefore, the screen keeps producing faulty(dark) output while the LED is blinking.